When trying to compile for nanoXplore synthesis fails, complaining
about those signals -- although they're unused.

Although not mentioned in section 5.2 of Wishbone B4 specification, when interfacing a pipelined
master to a standard slave, it is also necessary to make sure that if the slave asserts ACK/ERR/RTY
for more than one clock cycle (which a standard slave could do since, according to Rule 3.50 of
Wishbone B4, "the slave deasserts ACK/ERR/RTY in response to the negation of STB"), the master will
still only see a one cycle wide pulse.

wb_reg_link: add generics for instantiating wb adapters, since wb_reg_link works correctly only when used with pipelined wb interfaces

xwb_register_link: also register the CYC signal, otherwise STB remains active for one more cycle after CYC is dropped, which is not compliant with Wishbone

this is needed for VXS integration in which hdlmake is used to generate
a list of files used, these failes are alter copied to a Visual Elite
based project

Apologies for the double renaming, but it occured to me that the constant names were too generic and could cause conflicts.

This is introduced to better match the OHWR VHDL coding style [1].

Old names are preserved for backward compatibility.

[1]: https://www.ohwr.org/projects/vhdl-style

For the few peripherals where it was being used (eg. uart, spi, etc) the output port
has been renamed to "int_o".

The only peripheral that was not touched is "wb_eic.vhd", because this one is being used
by wbgen, and it would require users to update their wbgen tool as well. So, until a new
tool is introduced, wbgen-generated interrupt controllers will have an output port called
wb_int_o".

This reverts commit 49afba43.

This change was introduced in the masterFIP branch, but it can break many existing designs, so it is reverted.

The main state machine had an error whereby the wb_cyc and wb_stb
outputs were not assigned in the IDLE state.

This manifested itself as follows (output from telnet console):

%> writereg 1 100 0 # read to illegal address
  Not acknowledged!
%> readreg 1 4 # read from legal address returns NACK
  Not acknowledged
%> readreg 1 4 # next read from legal address returns right data
  Read data: 01234567

The bug was because the first writereg started a WB transfer from
an unexisting address, threw an error and returned to IDLE without
releasing the wb_cyc and wb_stb outputs in the process. This meant
that on the readreg command, the WB write access would still be in
progress and only on the readreg command, an error would clear the
wb_cyc and wb_stb, which released the transfer.

The error has been fixed by placing the clearing of wb_cyc and wb_stb
in the IDLE state.

the wishbone package

In wishbone_pkg.vhd, the new g_sdb_name generic was added to
xwb_crossbar instead of xwb_sdb_crossbar. Fixed