hdl: introduce generic dual rst async fifo (6d33dca2) · Commits · DAQ / Externals / general-cores · GitLab

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6d33dca2

Commit 6d33dca2 authored 6 years ago by Dimitris Lampridis

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hdl: introduce generic dual rst async fifo

parent 7faa55fe

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Changes 6

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modules/genrams/common/Manifest.py 6 additions, 3 deletions

modules/genrams/common/Manifest.py
modules/genrams/common/inferred_async_fifo_dual_rst.vhd 310 additions, 0 deletions

modules/genrams/common/inferred_async_fifo_dual_rst.vhd
modules/genrams/generic/Manifest.py 5 additions, 2 deletions

modules/genrams/generic/Manifest.py
modules/genrams/generic/generic_async_fifo_dual_rst.vhd 120 additions, 0 deletions

modules/genrams/generic/generic_async_fifo_dual_rst.vhd
modules/genrams/genram_pkg.vhd 38 additions, 0 deletions

modules/genrams/genram_pkg.vhd
modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd 43 additions, 19 deletions

modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd

with 522 additions and 24 deletions

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