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TFC-related update

Merged Vladimir Sidorenko requested to merge devel_vs into master
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@@ -47,6 +47,7 @@ entity gbt_fpga_common is
frame_clk_i : in std_logic;
rxwordclk_o : out std_logic_vector(NUM_LINKS-1 downto 0);
txwordclk_o : out std_logic_vector(NUM_LINKS-1 downto 0);
-- reference clocks for the MGT
-- must be 120 MHz
@@ -257,8 +258,9 @@ begin --========#### Architecture Body ####========--
--=================================================================================================--
-- Reverse the order of signals in the vector
rxwordclk_rev_gen: for i in 0 to NUM_LINKS-1 generate
wordClk_Inv_gen: for i in 0 to NUM_LINKS-1 generate
rxwordclk_o(i) <= mgt_rxwordclk_s(NUM_LINKS-i);
txwordclk_o(i) <= mgt_txwordclk_s(NUM_LINKS-i);
end generate;
-- according to gbtxManual
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