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trbnet
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master
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13
GbeLargeSctrl
blackcat
cbm_rich
deepsea
dirich5s1_new_reset_cdr_fix
fixedIP
master
default
protected
newGBE
retransmission
syncTRB
trb5_GbE
update
updated_ecp5_serdes
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1
oldGBE
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6
add missing fd broadcast to hub
master
master
update streaming accelerator to work with Hades CTS
Merge branch 'origin/updated_ecp5_serdes'
edge detect for fpga reboot
updated_ecp5_se…
updated_ecp5_serdes
add option to remove data output from CTS to save memory blocks in stand-alone designs
re-add small slow control buffer in GbE (4k instead of 64k)
add debug line for CV
fix reboot on reset sequence for ECP5
add ecp5 memory block 36x1k
fix old reset signal in sync_control, enable ECP5_RESET by default.
add missing changes to control signals
add ECP3 2x64k fifo
add ECP3 2x64k fifo
changed ECP5 Serdes settings
change reboot code to prevent race condition between timer and external reset
change timer range to ~15s
fix timer in ECP5 media interface
add an uptime timer to ecp5 media interfaces
changed few memories to use block RAM instead of distributed RAM by default
remove second tx reset from dual
add few debug ports to GbE
IPU reset makes release
fix syntax error
add hub status register 0x80++ to data bus at 4180++
add option to disable readout of word alignment in media interface
add generic to use ecp5 serdes with changed reset logic
revert change of LOL settings in ECP5 serdes
add further conditions to TRM reading in hub
add signal in advance of reboot to e.g. switch of Serdes / SFP
move unused files to old directory
add long reset signal for i2c bus
fix reset receiving in GbE endpoint
fix reset generation via GbE - failed in 1% of cases
add external slow control bus (flashsettings, debuguart) to streaming hub
add option to generate reset signal in ECP5 with falling edge to compensate for hold time violations
add files for large slowcontrol transfers
GbeLargeSctrl
GbeLargeSctrl
add support for TMP112 temperature sensor and its 13bit data format
dirich5s1 new reset routine and more stable CDR settings, mt
dirich5s1_new_r…
dirich5s1_new_reset_cdr_fix
add gbe ecp5 ram for new ping
add external reset to clock handler
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