ECP5 files for GbE support

gbe_trb/base/gbe_med_interface_onlyPCS.vhd

+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+use work.trb_net_gbe_components.all;
+use work.config.all;
+
+entity gbe_med_interface is
+	generic (
+		DO_SIMULATION : integer range 0 to 1;
+		NUMBER_OF_GBE_LINKS : integer range 1 to 4;
+		LINKS_ACTIVE : std_logic_vector(3 downto 0)
+	);
+	port (
+		RESET					: in	std_logic;
+		GSR_N					: in	std_logic;
+		CLK_SYS_IN				: in	std_logic;
+		CLK_125_OUT				: out	std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+		CLK_125_IN				: in	std_logic;
+		CLK_125_RX_OUT			: out	std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+		
+		-- MAC status and config
+		MAC_READY_CONF_OUT		: out	std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+		MAC_RECONF_IN			: in	std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+		MAC_AN_READY_OUT		: out	std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+		
+		-- MAC data interface
+		MAC_FIFOAVAIL_IN		: in	std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+		MAC_FIFOEOF_IN			: in	std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+		MAC_FIFOEMPTY_IN		: in	std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+		MAC_RX_FIFOFULL_IN		: in	std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+		
+		MAC_TX_DATA_IN			: in	std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
+		MAC_TX_READ_OUT			: out	std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+		MAC_TX_DISCRFRM_OUT		: out	std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+		MAC_TX_STAT_EN_OUT		: out	std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+		MAC_TX_STATS_OUT		: out	std_logic_vector(NUMBER_OF_GBE_LINKS * 31 - 1 downto 0);
+		MAC_TX_DONE_OUT			: out	std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+
+		MAC_RX_FIFO_ERR_OUT		: out	std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+		MAC_RX_STATS_OUT		: out	std_logic_vector(NUMBER_OF_GBE_LINKS * 32 - 1 downto 0);
+		MAC_RX_DATA_OUT			: out	std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
+		MAC_RX_WRITE_OUT		: out	std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+		MAC_RX_STAT_EN_OUT		: out	std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+		MAC_RX_EOF_OUT			: out	std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+		MAC_RX_ERROR_OUT		: out	std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+		
+		--SFP Connection
+		SD_RXD_P_IN				: in	std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+		SD_RXD_N_IN				: in	std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+		SD_TXD_P_OUT			: out	std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+		SD_TXD_N_OUT			: out	std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+		SD_PRSNT_N_IN			: in	std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+		SD_LOS_IN				: in	std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+		SD_TXDIS_OUT			: out	std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0); -- SFP disable
+		
+		--CONTROL INTERFACE
+		BUS_SCI_RX : in  CTRLBUS_RX;
+		BUS_SCI_TX : out CTRLBUS_TX;
+
+		DEBUG_OUT				: out	std_logic_vector(255 downto 0)		
+	);
+end entity gbe_med_interface;
+
+architecture RTL of gbe_med_interface is
+	
+	signal sd_rx_clk : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal sd_tx_kcntl_q, sd_tx_kcntl : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal sd_tx_data_q, sd_tx_data : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
+	signal xmit : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal sd_tx_correct_disp_q, sd_tx_correct_disp : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal sd_rx_data, sd_rx_data_q : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
+	signal sd_rx_kcntl, sd_rx_kcntl_q  : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal sd_rx_disp_error, sd_rx_disp_error_q : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal sd_rx_cv_error, sd_rx_cv_error_q : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal tx_power, rx_power : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal los, signal_detected : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal rx_cdr_lol: std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal tx_pll_lol, quad_rst : std_logic;
+	signal tx_pcs_rst, rx_pcs_rst, rx_serdes_rst : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	--signal rst_n : std_logic;
+	signal rx_clk_en : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal tx_clk_en : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal operational_rate : std_logic_vector(NUMBER_OF_GBE_LINKS * 2 - 1 downto 0);
+	signal an_complete : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal mr_page_rx : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal mr_lp_adv_ability : std_logic_vector(NUMBER_OF_GBE_LINKS * 16 - 1 downto 0);
+	signal mr_main_reset : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal mr_restart_an : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal mr_adv_ability : std_logic_vector(NUMBER_OF_GBE_LINKS * 16 - 1 downto 0);
+	signal mr_an_enable : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal pcs_rxd, pcs_rxd_q, pcs_rxd_qq : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
+	signal pcs_rx_en, pcs_rx_en_q, pcs_rx_en_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal pcs_rx_er, pcs_rx_er_q, pcs_rx_er_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal pcs_col, pcs_crs : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);  
+	signal pcs_txd, pcs_txd_q, pcs_txd_qq : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
+	signal pcs_tx_en, pcs_tx_en_q, pcs_tx_en_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal pcs_tx_er, pcs_tx_er_q, pcs_tx_er_qq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal tsm_hdataout_en_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal tsm_hready_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal tsm_hread_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal tsm_hwrite_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal tsm_hcs_n : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal tsm_hdata : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
+	signal tsm_haddr : std_logic_vector(NUMBER_OF_GBE_LINKS * 8 - 1 downto 0);
+	signal rx_compensation_err, an_link_ok : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	
+	signal synced_rst, ff : std_logic;
+	
+	signal fifo_eof_q, fifo_eof_qq, fifo_eof_qqq, fifo_eof_qqqq : std_logic_vector(NUMBER_OF_GBE_LINKS - 1 downto 0);
+	signal rsl_rx_rdy,rsl_tx_rdy : std_logic;
+	
+	signal sci_data_in_i : std_logic_vector(7 downto 0);
+	signal sci_addr_i : std_logic_vector(5 downto 0);
+  signal sci_data_out_i  : std_logic_vector(7 downto 0);
+  signal reset_n, sci_read_i, sci_write_i : std_logic;
+  signal sci_ch_i : std_logic_vector(4 downto 0);
+  signal wa_position        : std_logic_vector(15 downto 0) := x"FFFF";
+  signal wa_position_sel    : std_logic_vector(3 downto 0);
+  
+  signal stat_fsm_reset_i, stat_tx_control_i, stat_rx_control_i : std_logic_vector(31 downto 0);
+  signal cnt_125_dbg : unsigned(30 downto 0) := (others => '0');
+  
+begin
+	
+	rx_power <= "1111";
+	tx_power <= "1111";
+	
+	--rst_n <= not RESET;
+	
+	reset_sync : process(GSR_N, CLK_SYS_IN)
+	begin
+		if (GSR_N = '0') then
+			ff <= '0';
+			synced_rst <= '0';
+		elsif rising_edge(CLK_SYS_IN) then
+			ff <= '1';
+			synced_rst <= ff;
+		end if;
+	end process reset_sync;
+	
+	SD_TXDIS_OUT <= "0000";
+	
+	CLK_125_OUT    <= CLK_125_IN & CLK_125_IN & CLK_125_IN & CLK_125_IN;
+	CLK_125_RX_OUT <= sd_rx_clk;
+	
+	impl_gen : if DO_SIMULATION = 0 generate
+		
+		reset_n <= not RESET;
+		
+		serdes_ch1_gen : if FPGA_TYPE = 5 generate
+			gbe_serdes : entity work.sgmii_ecp5
+			port map(
+				hdoutp            => SD_TXD_P_OUT(0),--
+				hdoutn            => SD_TXD_N_OUT(0),--
+				hdinp             => SD_RXD_P_IN(0),--
+				hdinn             => SD_RXD_N_IN(0),--
+        rxrefclk          => CLK_125_IN,--
+        tx_pclk           => sd_rx_clk(0),--open,
+        txi_clk           => sd_rx_clk(0),--
+        txdata            => "00000000",--sd_tx_data_q(7 downto 0),--
+        tx_k              => "0",--sd_tx_kcntl_q(0 downto 0),--
+        xmit              => "1",--xmit(0 downto 0),--
+        tx_disp_correct   => "1",--sd_tx_correct_disp_q(0 downto 0),--
+        rxdata            => sd_rx_data(7 downto 0),--
+        rx_k              => sd_rx_kcntl(0 downto 0),--
+        rx_disp_err       => sd_rx_disp_error(0 downto 0),--
+        rx_cv_err         => sd_rx_cv_error(0 downto 0),--
+        signal_detect_c   => '0',--signal_detected(0),--
+        rx_los_low_s      => los(0),--
+        lsm_status_s      => signal_detected(0),
+        ctc_urun_s        => open,
+        ctc_orun_s        => open,
+        rx_cdr_lol_s      => rx_cdr_lol(0),
+        ctc_ins_s         => open,
+        ctc_del_s         => open,
+        sli_rst           => '0',
+        tx_pwrup_c        => tx_power(0),--
+        rx_pwrup_c        => rx_power(0),--
+        sci_wrdata        => sci_data_in_i,
+        sci_addr          => sci_addr_i,
+        sci_rddata        => sci_data_out_i,
+        sci_en_dual       => reset_n,
+        sci_sel_dual      => sci_ch_i(4),
+        sci_en            => reset_n,
+        sci_sel           => sci_ch_i(0),
+        sci_rd            => sci_read_i,
+        sci_wrn           => sci_write_i,
+        sci_int           => open,
+        cyawstn           => '0',
+        serdes_pdb        => '1', --powerdown control register
+        pll_refclki       => CLK_125_IN,--
+        rsl_disable				=> '0',--changed 2019.05.08;16:42
+        rsl_rst						=> '0',
+        serdes_rst_dual_c => '0',--
+        rst_dual_c        => quad_rst,--
+        tx_serdes_rst_c   => '0',--
+        tx_pcs_rst_c      => '0',--tx_pcs_rst(0),--
+        pll_lol           => tx_pll_lol,--
+        rsl_tx_rdy        => rsl_tx_rdy,
+        rx_serdes_rst_c   => rx_serdes_rst(0),--
+        rx_pcs_rst_c      => rx_pcs_rst(0),--
+        rsl_rx_rdy        => rsl_rx_rdy
+			);
+			end generate serdes_ch1_gen;
+			
+			wa_position_sel <= x"0";
+--TO DO  			
+			THE_PCS_RESET : entity work.pcs_sync_reset
+			generic map(
+			  IS_SYNC_SLAVE => 1,--????
+			  IS_TX_RESET   => 1
+			  )
+			port map(
+			  CLK_SYS     => CLK_SYS_IN,
+			  CLK_RXI     => sd_rx_clk(0),  --??correct??
+			  CLK_REF     => CLK_125_IN,
+			  RESET       => RESET,
+			  CLEAR       => '0',
+			  
+			  SFP_LOS     => SD_LOS_IN(0),
+			  TX_LOL      => tx_pll_lol,
+			  RX_CDR_LOL  => rx_cdr_lol(0),
+			  RX_LOS      => los(0),
+			  WA_POSITION => wa_position_sel,
+			  
+			  RX_SERDES_RST => rx_serdes_rst(0),
+			  RX_PCS_RST    => rx_pcs_rst(0),
+			  QUAD_RST      => quad_rst,
+			  TX_PCS_RST    => tx_pcs_rst(0),
+			  
+			  SERDES_RX_READY_IN => rsl_rx_rdy,
+			  SERDES_TX_READY_IN => rsl_tx_rdy,
+			  
+			  STAT_TX_CONTROL  => stat_tx_control_i,
+			  STAT_RX_CONTROL  => stat_rx_control_i,
+			  DEBUG_TX_CONTROL => open,--debug_tx_control_i,
+			  DEBUG_RX_CONTROL => open,--debug_rx_control_i,
+			  STAT_RESET       => stat_fsm_reset_i,
+			  DEBUG_OUT        => open--debug_med_sync_control_i
+			  );
+		
+		
+		
+			THE_SCI_READER : entity work.sci_reader
+			port map(
+			  CLK        => CLK_SYS_IN,
+			  RESET      => RESET,
+			  
+			  --SCI
+			  SCI_WRDATA  => sci_data_in_i,
+			  SCI_RDDATA  => sci_data_out_i,
+			  SCI_ADDR    => sci_addr_i,
+			  SCI_SEL     => sci_ch_i,
+			  SCI_RD      => sci_read_i,
+			  SCI_WR      => sci_write_i,
+			  
+			  WA_POS_OUT  => wa_position,
+			  
+			  --Slowcontrol
+			  BUS_RX      => BUS_SCI_RX,
+			  BUS_TX      => BUS_SCI_TX,
+			  
+			  MEDIA_STATUS_REG_IN(31 downto 0)   => stat_rx_control_i,
+			  MEDIA_STATUS_REG_IN(63 downto 32)  => stat_tx_control_i,
+			  MEDIA_STATUS_REG_IN(95 downto 64)  => stat_fsm_reset_i,
+			  --MEDIA_STATUS_REG_IN(127 downto 96) => stat_med,
+			  MEDIA_STATUS_REG_IN(255 downto 96) => (others => '0'),
+			  DEBUG_OUT   => open
+			  );
+			  
+			DEBUG_CLK : process(CLK_125_IN)
+			begin
+				if rising_edge(CLK_125_IN) then
+				  cnt_125_dbg <= cnt_125_dbg + 1;
+				end if;
+			end process DEBUG_CLK;
+			
+			DEBUG : process(CLK_SYS_IN)
+			begin
+				if rising_edge(CLK_SYS_IN) then
+					DEBUG_OUT(0) <= xmit(0);
+					DEBUG_OUT(1) <= los(0);
+					DEBUG_OUT(2) <= signal_detected(0);
+					DEBUG_OUT(3) <= tx_pll_lol;
+					DEBUG_OUT(4) <= rx_cdr_lol(0);
+					DEBUG_OUT(5) <= sd_rx_cv_error(0);
+					DEBUG_OUT(6) <= sd_rx_disp_error(0);
+					DEBUG_OUT(8 downto 7) <= operational_rate(1 downto 0);
+					DEBUG_OUT(9) <= rx_compensation_err(0);
+					DEBUG_OUT(10)<= an_link_ok(0);
+					DEBUG_OUT(11)<= MAC_READY_CONF_OUT(0);
+					DEBUG_OUT(12)<= an_complete(0);
+					DEBUG_OUT(13)<= rsl_rx_rdy;
+					DEBUG_OUT(14)<= rsl_tx_rdy;
+					DEBUG_OUT(15)<= cnt_125_dbg(30);
+				end if;
+			end process DEBUG;
+			
+		
+	end generate impl_gen;
+
+	sim_gen : if DO_SIMULATION =  1 generate
+		
+		process
+		begin
+			
+			MAC_AN_READY_OUT <= (others => '0');
+			wait for 2 us;
+			MAC_AN_READY_OUT <= (others => '1');
+			
+			wait;
+		end process;
+		
+		process(CLK_125_IN)
+		begin
+			if rising_edge(CLK_125_IN) then
+				MAC_TX_READ_OUT <= MAC_FIFOAVAIL_IN;
+				
+				fifo_eof_q <= MAC_FIFOEOF_IN;
+				fifo_eof_qq <= fifo_eof_q;
+				fifo_eof_qqq <= fifo_eof_qq;
+				fifo_eof_qqqq <= fifo_eof_qqq;
+				
+				MAC_TX_DONE_OUT <= fifo_eof_qqqq; -- MAC_FIFOEOF_IN;
+			end if;
+		end process;
+		
+		
+	end generate sim_gen;
+	
+
+end architecture RTL;

gbe_trb/ipcores/ecp5/fifo_2048x8x16.lpc

+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8BG756C
+SpeedGrade=8
+Package=CABGA756
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.8
+ModuleName=fifo_2048x8x16
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=04/24/2019
+Time=10:55:11
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=2048
+Width=9
+RDepth=1024
+RWidth=18
+regout=0
+ClockEn=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Async
+Reset1=Sync
+RDataCount=0
+WDataCount=0
+EnECC=0
+
+[Command]
+cmd_line= -w -n fifo_2048x8x16 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 2048 -width 9 -rwidth 18 -reset_rel SYNC -pe -1 -pf -1

gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.ipx

+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="fifo_64kx18x9_wcnt" module="FIFO_DC" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2021 11 15 10:18:44.720" version="5.8" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="fifo_64kx18x9_wcnt.lpc" type="lpc" modified="2021 11 15 10:18:42.000"/>
+		<File name="fifo_64kx18x9_wcnt.vhd" type="top_level_vhdl" modified="2021 11 15 10:18:42.000"/>
+		<File name="fifo_64kx18x9_wcnt_tmpl.vhd" type="template_vhdl" modified="2021 11 15 10:18:42.000"/>
+		<File name="tb_fifo_64kx18x9_wcnt_tmpl.vhd" type="testbench_vhdl" modified="2021 11 15 10:18:42.000"/>
+  </Package>
+</DiamondModule>

gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.lpc

+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8BG756C
+SpeedGrade=8
+Package=CABGA756
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.8
+ModuleName=fifo_64kx18x9_wcnt
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=11/15/2021
+Time=10:18:42
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=32768
+Width=18
+RDepth=65536
+RWidth=9
+regout=0
+ClockEn=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Async
+Reset1=Sync
+RDataCount=0
+WDataCount=1
+EnECC=0
+
+[Command]
+cmd_line= -w -n fifo_64kx18x9_wcnt -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 32768 -width 18 -rwidth 9 -reset_rel SYNC -pe -1 -pf -1 -fill

gbe_trb/ipcores/ecp5/fifo_8kx18x9_wcnt.lpc

+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8BG756C
+SpeedGrade=8
+Package=CABGA756
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.8
+ModuleName=fifo_8kx18x9_wcnt
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=04/30/2019
+Time=10:17:20
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=8192
+Width=18
+RDepth=16384
+RWidth=9
+regout=0
+ClockEn=0
+CtrlByRdEn=0
+EmpFlg=1
+PeMode=Dynamic - Single Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Dynamic - Single Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Async
+Reset1=Sync
+RDataCount=0
+WDataCount=1
+EnECC=0
+
+[Command]
+cmd_line= -w -n fifo_8kx18x9_wcnt -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -depth 8192 -width 18 -rwidth 9 -reset_rel SYNC -pe 0 -pf 0 -fill

gbe_trb/ipcores/ecp5/ip_mem.lpc

+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8BG756C
+SpeedGrade=8
+Package=CABGA756
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=RAM_DP_TRUE
+CoreRevision=7.5
+ModuleName=ip_mem
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=04/24/2019
+Time=11:30:09
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+RAddress=256
+RData=32
+WAddress=256
+WData=32
+ROutputEn=0
+RClockEn=0
+WOutputEn=1
+WClockEn=0
+enByte=0
+ByteSize=9
+Optimization=Speed
+Reset=Sync
+Reset1=Sync
+Init=mem
+MemFile=/home/adrian/git/trbnet/gbe2_ecp3/ipcores/ip_mem.mem
+MemFormat=orca
+EnECC=0
+Pipeline=0
+WriteA=Normal
+WriteB=Normal
+init_data=0
+
+[FilesGenerated]
+/home/adrian/git/trbnet/gbe2_ecp3/ipcores/ip_mem.mem=mem
+
+[Command]
+cmd_line= -w -n ip_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ramdp -device LFE5UM-85F -aaddr_width 8 -widtha 32 -baddr_width 8 -widthb 32 -anum_words 256 -bnum_words 256 -outdataB REGISTERED -cascade -1 -resetmode SYNC -sync_reset -memfile /home/adrian/git/trbnet/gbe2_ecp3/ipcores/ip_mem.mem -memformat orca -writemodeA NORMAL -writemodeB NORMAL

gbe_trb/media/ecp5/pcs_sync_reset.vhd

+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.med_sync_define.all;
+
+entity pcs_sync_reset is
+  generic(
+    IS_SYNC_SLAVE : integer := 1;
+    IS_TX_RESET   : integer := 1
+    );
+  port(
+    CLK_SYS     : in  std_logic;
+    CLK_RXI     : in  std_logic;
+    CLK_REF     : in  std_logic;
+    RESET       : in  std_logic;
+    CLEAR       : in  std_logic;
+    
+    SFP_LOS     : in  std_logic;
+    TX_LOL      : in  std_logic;
+    RX_CDR_LOL  : in  std_logic;
+    RX_LOS      : in  std_logic;
+    WA_POSITION : in  std_logic_vector(3 downto 0);
+    
+    RX_SERDES_RST : out std_logic;
+    RX_PCS_RST    : out std_logic;
+    QUAD_RST      : out std_logic;
+    TX_PCS_RST    : out std_logic;
+    
+    SERDES_RX_READY_IN : in std_logic := '1';
+    SERDES_TX_READY_IN : in std_logic := '1';
+    
+    STAT_TX_CONTROL  : out std_logic_vector(31 downto 0);
+    STAT_RX_CONTROL  : out std_logic_vector(31 downto 0);
+    DEBUG_TX_CONTROL : out std_logic_vector(31 downto 0);
+    DEBUG_RX_CONTROL : out std_logic_vector(31 downto 0);
+    STAT_RESET       : out std_logic_vector(31 downto 0);
+    DEBUG_OUT        : out std_logic_vector(31 downto 0)
+    );
+end entity;
+
+
+architecture pcs_sync_reset_arch of pcs_sync_reset is
+
+signal rx_fsm_state : std_logic_vector(3 downto 0);
+signal tx_fsm_state : std_logic_vector(3 downto 0);
+signal wa_position_rx : std_logic_vector(3 downto 0);
+signal start_timer       : unsigned(21 downto 0) := (others => '0');
+
+signal request_retr_i     : std_logic;
+signal start_retr_i       : std_logic;
+signal request_retr_position_i  : std_logic_vector(7 downto 0);
+signal start_retr_position_i    : std_logic_vector(7 downto 0);
+signal rx_dlm_i           : std_logic;
+
+signal timer                  : unsigned(20 downto 0);
+signal sd_los_i               : std_logic;
+
+signal rx_allow               : std_logic;
+signal tx_allow               : std_logic;
+signal got_link_ready_i       : std_logic;
+signal make_link_reset_i      : std_logic;
+signal send_link_reset_i      : std_logic;
+signal make_link_reset_real_i : std_logic := '0';
+signal make_link_reset_sys_i  : std_logic := '0';
+signal send_link_reset_real_i : std_logic := '0';
+signal send_link_reset_sys_i  : std_logic := '0';
+
+signal reset_i, rst_n, rst_n_tx : std_logic;
+signal finished_reset_rx, finished_reset_rx_q : std_logic;
+signal finished_reset_tx, finished_reset_tx_q : std_logic;
+
+begin
+
+rst_n_tx  <=       not (CLEAR or sd_los_i or make_link_reset_real_i or RESET) when (IS_SYNC_SLAVE = 1 and IS_TX_RESET = 1)
+              else not (CLEAR or make_link_reset_real_i or RESET);
+
+
+
+rst_n     <= not (CLEAR or sd_los_i or make_link_reset_real_i or RESET);
+reset_i   <=     (RESET or sd_los_i or make_link_reset_real_i);
+
+
+
+
+-------------------------------------------------      
+-- Reset FSM & Link states
+-------------------------------------------------      
+THE_RX_FSM : rx_reset_fsm
+  port map(
+    RST_N                => rst_n,
+    RX_REFCLK            => CLK_REF,
+    TX_PLL_LOL_QD_S      => TX_LOL,
+    RX_SERDES_RST_CH_C   => RX_SERDES_RST,
+    RX_CDR_LOL_CH_S      => RX_CDR_LOL,
+    RX_LOS_LOW_CH_S      => RX_LOS,
+    RX_PCS_RST_CH_C      => RX_PCS_RST,
+    WA_POSITION          => wa_position_rx,
+    NORMAL_OPERATION_OUT => finished_reset_rx,
+    STATE_OUT            => rx_fsm_state
+    );
+    
+THE_TX_FSM : tx_reset_fsm
+  port map(
+    RST_N                => rst_n_tx,
+    TX_REFCLK            => CLK_REF,
+    TX_PLL_LOL_QD_S      => TX_LOL,
+    RST_QD_C             => QUAD_RST,
+    TX_PCS_RST_CH_C      => TX_PCS_RST,
+    NORMAL_OPERATION_OUT => finished_reset_tx,
+    STATE_OUT            => tx_fsm_state
+    );
+
+    
+SYNC_WA_POSITION : process begin
+  wait until rising_edge(CLK_REF);
+  if IS_SYNC_SLAVE = 1 then
+    wa_position_rx <= WA_POSITION;
+  else
+    wa_position_rx <= x"0";
+  end if;
+end process;    
+    
+-------------------------------------------------      
+-- RX & TX allow
+-------------------------------------------------  
+--Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable
+PROC_ALLOW : process begin
+  wait until rising_edge(CLK_SYS);
+  if finished_reset_rx_q = '1'  --SERDES_RX_READY_IN= '1' --and 
+            and (IS_SYNC_SLAVE = 1 or start_timer(start_timer'left) = '1') then
+    rx_allow <= '1';
+  else
+    rx_allow <= '0';
+  end if;
+  if  --SERDES_RX_READY_IN = '1' and SERDES_TX_READY_IN = '1'  
+        finished_reset_tx_q = '1' and finished_reset_rx_q = '1' 
+            and (IS_SYNC_SLAVE = 1 or start_timer(start_timer'left) = '1') then
+    tx_allow <= '1';
+  else
+    tx_allow <= '0';
+  end if;
+end process;
+
+
+  link_reset_fin_tx  : signal_sync port map(RESET => '0',CLK0 => CLK_SYS, CLK1 => CLK_SYS,
+                                          D_IN(0)  => finished_reset_tx, 
+                                          D_OUT(0) => finished_reset_tx_q);
+  link_reset_fin_rx  : signal_sync port map(RESET => '0',CLK0 => CLK_SYS, CLK1 => CLK_SYS,
+                                          D_IN(0)  => finished_reset_rx, 
+                                          D_OUT(0) => finished_reset_rx_q);
+
+
+PROC_START_TIMER : process begin
+  wait until rising_edge(CLK_SYS);
+ -- if got_link_ready_i = '1' then
+  if finished_reset_tx_q = '1' and finished_reset_rx_q = '1'  then
+    if start_timer(start_timer'left) = '0' then
+      start_timer <= start_timer + 1;
+    end if;  
+  else
+    start_timer <= (others => '0');
+  end if;
+end process;
+        
+-------------------------------------------------      
+-- Status signals
+-------------------------------------------------   
+
+STAT_RESET(3 downto 0)   <= rx_fsm_state;
+STAT_RESET(7 downto 4)   <= tx_fsm_state;
+STAT_RESET(8)            <= tx_allow;
+STAT_RESET(9)            <= rx_allow;
+STAT_RESET(15 downto 10) <= (others => '0');
+STAT_RESET(16)           <= RX_CDR_LOL;
+STAT_RESET(17)           <= RX_LOS;
+STAT_RESET(18)           <= '0';--QUAD_RST; --RX_PCS_RST;
+STAT_RESET(19)           <= '0';--TX_PCS_RST;
+STAT_RESET(20)           <= TX_LOL;
+STAT_RESET(21)           <= rst_n;
+STAT_RESET(22)           <= rst_n_tx;
+STAT_RESET(30 downto 23) <= (others => '0');
+STAT_RESET(31) <= start_timer(start_timer'left);
+
+
+gen_link_reset : if IS_SYNC_SLAVE = 1 generate
+  link_reset_pulse : pulse_sync port map( CLK_A_IN => CLK_RXI, CLK_B_IN => CLK_SYS,
+                                          PULSE_A_IN => make_link_reset_i, 
+                                          PULSE_B_OUT => make_link_reset_sys_i);
+  link_reset_send  : signal_sync port map(RESET => '0',CLK0 => CLK_RXI,CLK1 => CLK_SYS,
+                                          D_IN(0)  => send_link_reset_i, 
+                                          D_OUT(0) => send_link_reset_sys_i);
+end generate;
+
+make_link_reset_real_i <= make_link_reset_sys_i or sd_los_i when IS_SYNC_SLAVE = 1
+                          else '0';
+send_link_reset_real_i <=  send_link_reset_sys_i when IS_SYNC_SLAVE = 1
+                          else '0';
+
+sd_los_i <= SFP_LOS when rising_edge(CLK_SYS);
+
+
+DEBUG_OUT(0) <= tx_allow;
+DEBUG_OUT(1) <= rx_allow;
+DEBUG_OUT(2) <= sd_los_i;
+DEBUG_OUT(3) <= '0'; --DEBUG_RX_CONTROL(4);
+
+end architecture;

gbe_trb/media/ecp5/pcstest/sgmii_ecp5.lpc

+[Device]
+Family=ecp5um
+OperatingCondition=COM
+Package=CABGA756
+PartName=LFE5UM-85F-8BG756C
+PartType=LFE5UM-85F
+SpeedGrade=8
+Status=P
+[IP]
+CoreName=PCS
+CoreRevision=8.2
+CoreStatus=Demo
+CoreType=LPM
+Date=05/09/2019
+ModuleName=sgmii_ecp5
+ParameterFileVersion=1.0
+SourceFormat=vhdl
+Time=16:52:08
+VendorName=Lattice Semiconductor Corporation
+[Parameters]
+;ACHARA=0 00H
+;ACHARB=0 00H
+;ACHARM=0 00H
+;RXMCAENABLE=Disabled
+CDRLOLACTION=Full Recalibration
+CDRLOLRANGE=3
+CDR_MAX_RATE=1.25
+CDR_MULT=10X
+CDR_REF_RATE=125.0000
+CH_MODE=Rx and Tx
+Destination=Synplicity
+EDIF=1
+Expression=BusA(0 to 7)
+IO=0
+IO_TYPE=GbE
+LEQ=0
+LOOPBACK=Disabled
+LOSPORT=Enabled
+NUM_CHS=1
+Order=Big Endian [MSB:LSB]
+PPORT_RX_RDY=Enabled
+PPORT_TX_RDY=Enabled
+PROTOCOL=GbE
+PWAIT_RX_RDY=3000
+PWAIT_TX_RDY=3000
+RCSRC=Disabled
+REFCLK_RATE=125.0000
+RSTSEQSEL=Enabled
+RX8B10B=Enabled
+RXCOMMAA=1010000011
+RXCOMMAB=0101111100
+RXCOMMAM=1111111111
+RXCOUPLING=AC
+RXCTC=Enabled
+RXCTCBYTEN=0 00H
+RXCTCBYTEN1=0 00H
+RXCTCBYTEN2=1 BCH
+RXCTCBYTEN3=0 50H
+RXCTCMATCHPATTERN=M2-S2
+RXDIFFTERM=50 ohms
+RXFIFO_ENABLE=Enabled
+RXINVPOL=Non-invert
+RXLDR=Off
+RXLOSTHRESHOLD=4
+RXLSM=Enabled
+RXSC=K28P5
+RXWA=Barrel Shift
+RX_DATA_WIDTH=8/10-Bit
+RX_FICLK_RATE=125.0000
+RX_LINE_RATE=1.2500
+RX_RATE_DIV=Full Rate
+SCIPORT=Enabled
+SOFTLOL=Enabled
+TX8B10B=Enabled
+TXAMPLITUDE=1100
+TXDEPOST=Disabled
+TXDEPRE=Disabled
+TXDIFFTERM=50 ohms
+TXFIFO_ENABLE=Enabled
+TXINVPOL=Non-invert
+TXLDR=Off
+TXPLLLOLTHRESHOLD=1
+TXPLLMULT=10X
+TX_DATA_WIDTH=8/10-Bit
+TX_FICLK_RATE=125.0000
+TX_LINE_RATE=1.2500
+TX_MAX_RATE=1.25
+TX_RATE_DIV=Full Rate
+VHDL=1
+Verilog=0
+[FilesGenerated]
+sgmii_ecp5.pp=pp
+sgmii_ecp5.sym=sym
+sgmii_ecp5.tft=tft
+sgmii_ecp5.txt=pcs_module
+[SYSTEMPNR]
+LN0=DCU1_CH1