Merge branch 'master' into cbm_rich

gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd

@@ -554,7 +554,8 @@ begin
 		
 		when LOAD_TO_HUB =>
 			state <= x"4";
-			if (rx_fifo_q(17) = '1') then
+--			if (rx_fifo_q(17) = '1') then
+			if ((rx_fifo_q(17) = '1') and (GSC_INIT_READ_IN = '1')) then
 				if (reset_detected = '1') then
 					dissect_next_state <= CLEANUP;
 				else

media_interfaces/ecp5/240MHz/chan0_0/serdes_sync_0.lpc

+[Device]
+Family=ecp5um
+OperatingCondition=COM
+Package=CABGA756
+PartName=LFE5UM-85F-8BG756C
+PartType=LFE5UM-85F
+SpeedGrade=8
+Status=P
+[IP]
+CoreName=PCS
+CoreRevision=8.2
+CoreStatus=Demo
+CoreType=LPM
+Date=04/27/2022
+ModuleName=serdes_sync_0
+ParameterFileVersion=1.0
+SourceFormat=VHDL
+Time=13:12:53
+VendorName=Lattice Semiconductor Corporation
+[Parameters]
+;ACHARA=0 00H
+;ACHARB=0 00H
+;ACHARM=0 00H
+;RXMCAENABLE=Disabled
+CDRLOLACTION=Full Recalibration
+CDRLOLRANGE=3
+CDR_MAX_RATE=2.4
+CDR_MULT=10X
+CDR_REF_RATE=240.0000
+CH_MODE=Rx and Tx
+Destination=Synplicity
+EDIF=1
+Expression=BusA(0 to 7)
+IO=0
+IO_TYPE=G8B10B
+LEQ=Disabled
+LOOPBACK=Disabled
+LOSPORT=Enabled
+NUM_CHS=1
+Order=Big Endian [MSB:LSB]
+PPORT_RX_RDY=Enabled
+PPORT_TX_RDY=Enabled
+PROTOCOL=G8B10B
+PWAIT_RX_RDY=3000
+PWAIT_TX_RDY=3000
+RCSRC=Disabled
+REFCLK_RATE=240.0000
+RSTSEQSEL=Enabled
+RX8B10B=Enabled
+RXCOMMAA=0010000011
+RXCOMMAB=0001111100
+RXCOMMAM=0011111111
+RXCOUPLING=AC
+RXCTC=Disabled
+RXCTCBYTEN=0 00H
+RXCTCBYTEN1=0 00H
+RXCTCBYTEN2=0 00H
+RXCTCBYTEN3=0 00H
+RXCTCMATCHPATTERN=M4-S4
+RXDIFFTERM=50 ohms
+RXFIFO_ENABLE=Enabled
+RXINVPOL=Non-invert
+RXLDR=Off
+RXLOSTHRESHOLD=0
+RXLSM=Enabled
+RXSC=K28P157
+RXWA=Barrel Shift
+RX_DATA_WIDTH=8/10-Bit
+RX_FICLK_RATE=240.0000
+RX_LINE_RATE=2.4000
+RX_RATE_DIV=Full Rate
+SCIPORT=Enabled
+SOFTLOL=Enabled
+TX8B10B=Enabled
+TXAMPLITUDE=800
+TXDEPOST=Disabled
+TXDEPRE=Disabled
+TXDIFFTERM=50 ohms
+TXFIFO_ENABLE=Enabled
+TXINVPOL=Non-invert
+TXLDR=Off
+TXPLLLOLTHRESHOLD=1
+TXPLLMULT=10X
+TX_DATA_WIDTH=8/10-Bit
+TX_FICLK_RATE=240.0000
+TX_LINE_RATE=2.4000
+TX_MAX_RATE=2.4
+TX_RATE_DIV=Full Rate
+VHDL=1
+Verilog=0
+[FilesGenerated]
+serdes_sync_0.pp=pp
+serdes_sync_0.sym=sym
+serdes_sync_0.tft=tft
+serdes_sync_0.txt=pcs_module
+[SYSTEMPNR]
+LN0=DCU0_CH0

media_interfaces/ecp5/240MHz/chan0_0/serdes_sync_0_ngd.asd

+[ActiveSupport NGD]

media_interfaces/ecp5/240MHz/chan0_1/serdes_sync_0.lpc

+[Device]
+Family=ecp5um
+OperatingCondition=COM
+Package=CABGA756
+PartName=LFE5UM-85F-8BG756C
+PartType=LFE5UM-85F
+SpeedGrade=8
+Status=P
+[IP]
+CoreName=PCS
+CoreRevision=8.2
+CoreStatus=Demo
+CoreType=LPM
+Date=04/27/2022
+ModuleName=serdes_sync_0
+ParameterFileVersion=1.0
+SourceFormat=VHDL
+Time=13:12:53
+VendorName=Lattice Semiconductor Corporation
+[Parameters]
+;ACHARA=0 00H
+;ACHARB=0 00H
+;ACHARM=0 00H
+;RXMCAENABLE=Disabled
+CDRLOLACTION=Full Recalibration
+CDRLOLRANGE=3
+CDR_MAX_RATE=2.4
+CDR_MULT=10X
+CDR_REF_RATE=240.0000
+CH_MODE=Rx and Tx
+Destination=Synplicity
+EDIF=1
+Expression=BusA(0 to 7)
+IO=0
+IO_TYPE=G8B10B
+LEQ=Disabled
+LOOPBACK=Disabled
+LOSPORT=Enabled
+NUM_CHS=1
+Order=Big Endian [MSB:LSB]
+PPORT_RX_RDY=Enabled
+PPORT_TX_RDY=Enabled
+PROTOCOL=G8B10B
+PWAIT_RX_RDY=3000
+PWAIT_TX_RDY=3000
+RCSRC=Disabled
+REFCLK_RATE=240.0000
+RSTSEQSEL=Enabled
+RX8B10B=Enabled
+RXCOMMAA=0010000011
+RXCOMMAB=0001111100
+RXCOMMAM=0011111111
+RXCOUPLING=AC
+RXCTC=Disabled
+RXCTCBYTEN=0 00H
+RXCTCBYTEN1=0 00H
+RXCTCBYTEN2=0 00H
+RXCTCBYTEN3=0 00H
+RXCTCMATCHPATTERN=M4-S4
+RXDIFFTERM=50 ohms
+RXFIFO_ENABLE=Enabled
+RXINVPOL=Non-invert
+RXLDR=Off
+RXLOSTHRESHOLD=0
+RXLSM=Enabled
+RXSC=K28P157
+RXWA=Barrel Shift
+RX_DATA_WIDTH=8/10-Bit
+RX_FICLK_RATE=240.0000
+RX_LINE_RATE=2.4000
+RX_RATE_DIV=Full Rate
+SCIPORT=Enabled
+SOFTLOL=Enabled
+TX8B10B=Enabled
+TXAMPLITUDE=800
+TXDEPOST=Disabled
+TXDEPRE=Disabled
+TXDIFFTERM=50 ohms
+TXFIFO_ENABLE=Enabled
+TXINVPOL=Non-invert
+TXLDR=Off
+TXPLLLOLTHRESHOLD=1
+TXPLLMULT=10X
+TX_DATA_WIDTH=8/10-Bit
+TX_FICLK_RATE=240.0000
+TX_LINE_RATE=2.4000
+TX_MAX_RATE=2.4
+TX_RATE_DIV=Full Rate
+VHDL=1
+Verilog=0
+[FilesGenerated]
+serdes_sync_0.pp=pp
+serdes_sync_0.sym=sym
+serdes_sync_0.tft=tft
+serdes_sync_0.txt=pcs_module
+[SYSTEMPNR]
+LN0=DCU0_CH1

media_interfaces/ecp5/240MHz/chan0_1/serdes_sync_0_ngd.asd

+[ActiveSupport NGD]

media_interfaces/ecp5/240MHz/chan1_0/serdes_sync_2.lpc

+[Device]
+Family=ecp5um
+OperatingCondition=COM
+Package=CABGA756
+PartName=LFE5UM-85F-8BG756C
+PartType=LFE5UM-85F
+SpeedGrade=8
+Status=P
+[IP]
+CoreName=PCS
+CoreRevision=8.2
+CoreStatus=Demo
+CoreType=LPM
+Date=05/04/2022
+ModuleName=serdes_sync_2
+ParameterFileVersion=1.0
+SourceFormat=VHDL
+Time=11:10:31
+VendorName=Lattice Semiconductor Corporation
+[Parameters]
+;ACHARA=0 00H
+;ACHARB=0 00H
+;ACHARM=0 00H
+;RXMCAENABLE=Disabled
+CDRLOLACTION=Full Recalibration
+CDRLOLRANGE=3
+CDR_MAX_RATE=2.4
+CDR_MULT=10X
+CDR_REF_RATE=240.0000
+CH_MODE=Rx and Tx
+Destination=Synplicity
+EDIF=1
+Expression=BusA(0 to 7)
+IO=0
+IO_TYPE=G8B10B
+LEQ=Disabled
+LOOPBACK=Disabled
+LOSPORT=Enabled
+NUM_CHS=1
+Order=Big Endian [MSB:LSB]
+PPORT_RX_RDY=Enabled
+PPORT_TX_RDY=Enabled
+PROTOCOL=G8B10B
+PWAIT_RX_RDY=3000
+PWAIT_TX_RDY=3000
+RCSRC=Disabled
+REFCLK_RATE=240.0000
+RSTSEQSEL=Enabled
+RX8B10B=Enabled
+RXCOMMAA=0010000011
+RXCOMMAB=0001111100
+RXCOMMAM=0011111111
+RXCOUPLING=AC
+RXCTC=Disabled
+RXCTCBYTEN=0 00H
+RXCTCBYTEN1=0 00H
+RXCTCBYTEN2=0 00H
+RXCTCBYTEN3=0 00H
+RXCTCMATCHPATTERN=M4-S4
+RXDIFFTERM=50 ohms
+RXFIFO_ENABLE=Enabled
+RXINVPOL=Non-invert
+RXLDR=Off
+RXLOSTHRESHOLD=0
+RXLSM=Enabled
+RXSC=K28P157
+RXWA=Barrel Shift
+RX_DATA_WIDTH=8/10-Bit
+RX_FICLK_RATE=240.0000
+RX_LINE_RATE=2.4000
+RX_RATE_DIV=Full Rate
+SCIPORT=Enabled
+SOFTLOL=Enabled
+TX8B10B=Enabled
+TXAMPLITUDE=800
+TXDEPOST=Disabled
+TXDEPRE=Disabled
+TXDIFFTERM=50 ohms
+TXFIFO_ENABLE=Enabled
+TXINVPOL=Non-invert
+TXLDR=Off
+TXPLLLOLTHRESHOLD=1
+TXPLLMULT=10X
+TX_DATA_WIDTH=8/10-Bit
+TX_FICLK_RATE=240.0000
+TX_LINE_RATE=2.4000
+TX_MAX_RATE=2.4
+TX_RATE_DIV=Full Rate
+VHDL=1
+Verilog=0
+[FilesGenerated]
+serdes_sync_2.pp=pp
+serdes_sync_2.sym=sym
+serdes_sync_2.tft=tft
+serdes_sync_2.txt=pcs_module
+[SYSTEMPNR]
+LN0=DCU1_CH0

media_interfaces/ecp5/240MHz/chan1_0/serdes_sync_2_ngd.asd

+[ActiveSupport NGD]

media_interfaces/ecp5/240MHz/pcs2_240.vhd

+
+
+--
+-- Verific VHDL Description of module pcs_240
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity pcs2_240 is
+    port (serdes_sync_0_rx_cv_err: out std_logic_vector(0 downto 0);
+        serdes_sync_0_rx_disp_err: out std_logic_vector(0 downto 0);
+        serdes_sync_0_rx_k: out std_logic_vector(0 downto 0);
+        serdes_sync_0_rxdata: out std_logic_vector(7 downto 0);
+        serdes_sync_0_sci_addr: in std_logic_vector(5 downto 0);
+        serdes_sync_0_sci_rddata: out std_logic_vector(7 downto 0);
+        serdes_sync_0_sci_wrdata: in std_logic_vector(7 downto 0);
+        serdes_sync_0_tx_disp_sel: in std_logic_vector(0 downto 0);
+        serdes_sync_0_tx_force_disp: in std_logic_vector(0 downto 0);
+        serdes_sync_0_tx_k: in std_logic_vector(0 downto 0);
+        serdes_sync_0_txdata: in std_logic_vector(7 downto 0);
+        serdes_sync_0_cyawstn: in std_logic;
+        serdes_sync_0_hdinn: in std_logic;
+        serdes_sync_0_hdinp: in std_logic;
+        serdes_sync_0_hdoutn: out std_logic;
+        serdes_sync_0_hdoutp: out std_logic;
+        serdes_sync_0_lsm_status_s: out std_logic;
+        serdes_sync_0_pll_lol: out std_logic;
+        serdes_sync_0_pll_refclki: in std_logic;
+        serdes_sync_0_rsl_disable: in std_logic;
+        serdes_sync_0_rsl_rst: in std_logic;
+        serdes_sync_0_rsl_rx_rdy: out std_logic;
+        serdes_sync_0_rsl_tx_rdy: out std_logic;
+        serdes_sync_0_rst_dual_c: in std_logic;
+        serdes_sync_0_rx_cdr_lol_s: out std_logic;
+        serdes_sync_0_rx_los_low_s: out std_logic;
+        serdes_sync_0_rx_pclk: out std_logic;
+        serdes_sync_0_rx_pcs_rst_c: in std_logic;
+        serdes_sync_0_rx_pwrup_c: in std_logic;
+        serdes_sync_0_rx_serdes_rst_c: in std_logic;
+        serdes_sync_0_rxrefclk: in std_logic;
+        serdes_sync_0_sci_en: in std_logic;
+        serdes_sync_0_sci_en_dual: in std_logic;
+        serdes_sync_0_sci_int: out std_logic;
+        serdes_sync_0_sci_rd: in std_logic;
+        serdes_sync_0_sci_sel: in std_logic;
+        serdes_sync_0_sci_sel_dual: in std_logic;
+        serdes_sync_0_sci_wrn: in std_logic;
+        serdes_sync_0_serdes_pdb: in std_logic;
+        serdes_sync_0_serdes_rst_dual_c: in std_logic;
+        serdes_sync_0_signal_detect_c: in std_logic;
+        serdes_sync_0_tx_idle_c: in std_logic;
+        serdes_sync_0_tx_pclk: out std_logic;
+        serdes_sync_0_tx_pcs_rst_c: in std_logic;
+        serdes_sync_0_tx_pwrup_c: in std_logic;
+        serdes_sync_0_tx_serdes_rst_c: in std_logic
+    );
+    
+end entity pcs2_240; -- sbp_module=true 
+
+architecture pcs2_240 of pcs2_240 is 
+    component serdes_sync_2 is
+        port (rx_cv_err: out std_logic_vector(0 downto 0);
+            rx_disp_err: out std_logic_vector(0 downto 0);
+            rx_k: out std_logic_vector(0 downto 0);
+            rxdata: out std_logic_vector(7 downto 0);
+            sci_addr: in std_logic_vector(5 downto 0);
+            sci_rddata: out std_logic_vector(7 downto 0);
+            sci_wrdata: in std_logic_vector(7 downto 0);
+            tx_disp_sel: in std_logic_vector(0 downto 0);
+            tx_force_disp: in std_logic_vector(0 downto 0);
+            tx_k: in std_logic_vector(0 downto 0);
+            txdata: in std_logic_vector(7 downto 0);
+            cyawstn: in std_logic;
+            hdinn: in std_logic;
+            hdinp: in std_logic;
+            hdoutn: out std_logic;
+            hdoutp: out std_logic;
+            lsm_status_s: out std_logic;
+            pll_lol: out std_logic;
+            pll_refclki: in std_logic;
+            rsl_disable: in std_logic;
+            rsl_rst: in std_logic;
+            rsl_rx_rdy: out std_logic;
+            rsl_tx_rdy: out std_logic;
+            rst_dual_c: in std_logic;
+            rx_cdr_lol_s: out std_logic;
+            rx_los_low_s: out std_logic;
+            rx_pclk: out std_logic;
+            rx_pcs_rst_c: in std_logic;
+            rx_pwrup_c: in std_logic;
+            rx_serdes_rst_c: in std_logic;
+            rxrefclk: in std_logic;
+            sci_en: in std_logic;
+            sci_en_dual: in std_logic;
+            sci_int: out std_logic;
+            sci_rd: in std_logic;
+            sci_sel: in std_logic;
+            sci_sel_dual: in std_logic;
+            sci_wrn: in std_logic;
+            serdes_pdb: in std_logic;
+            serdes_rst_dual_c: in std_logic;
+            signal_detect_c: in std_logic;
+            sli_rst: in std_logic;
+            tx_idle_c: in std_logic;
+            tx_pclk: out std_logic;
+            tx_pcs_rst_c: in std_logic;
+            tx_pwrup_c: in std_logic;
+            tx_serdes_rst_c: in std_logic
+        );
+        
+    end component serdes_sync_2; -- not_need_bbox=true 
+    
+    
+    signal sli_rst_wire0,gnd : std_logic; 
+begin
+    sli_rst_wire0 <= serdes_sync_0_serdes_rst_dual_c OR  serdes_sync_0_tx_serdes_rst_c OR  (NOT serdes_sync_0_serdes_pdb) OR  (NOT serdes_sync_0_tx_pwrup_c);
+    serdes_sync_0_inst: component serdes_sync_2 port map (rx_cv_err(0)=>serdes_sync_0_rx_cv_err(0),
+            rx_disp_err(0)=>serdes_sync_0_rx_disp_err(0),rx_k(0)=>serdes_sync_0_rx_k(0),
+            rxdata(7)=>serdes_sync_0_rxdata(7),rxdata(6)=>serdes_sync_0_rxdata(6),
+            rxdata(5)=>serdes_sync_0_rxdata(5),rxdata(4)=>serdes_sync_0_rxdata(4),
+            rxdata(3)=>serdes_sync_0_rxdata(3),rxdata(2)=>serdes_sync_0_rxdata(2),
+            rxdata(1)=>serdes_sync_0_rxdata(1),rxdata(0)=>serdes_sync_0_rxdata(0),
+            sci_addr(5)=>serdes_sync_0_sci_addr(5),sci_addr(4)=>serdes_sync_0_sci_addr(4),
+            sci_addr(3)=>serdes_sync_0_sci_addr(3),sci_addr(2)=>serdes_sync_0_sci_addr(2),
+            sci_addr(1)=>serdes_sync_0_sci_addr(1),sci_addr(0)=>serdes_sync_0_sci_addr(0),
+            sci_rddata(7)=>serdes_sync_0_sci_rddata(7),sci_rddata(6)=>serdes_sync_0_sci_rddata(6),
+            sci_rddata(5)=>serdes_sync_0_sci_rddata(5),sci_rddata(4)=>serdes_sync_0_sci_rddata(4),
+            sci_rddata(3)=>serdes_sync_0_sci_rddata(3),sci_rddata(2)=>serdes_sync_0_sci_rddata(2),
+            sci_rddata(1)=>serdes_sync_0_sci_rddata(1),sci_rddata(0)=>serdes_sync_0_sci_rddata(0),
+            sci_wrdata(7)=>serdes_sync_0_sci_wrdata(7),sci_wrdata(6)=>serdes_sync_0_sci_wrdata(6),
+            sci_wrdata(5)=>serdes_sync_0_sci_wrdata(5),sci_wrdata(4)=>serdes_sync_0_sci_wrdata(4),
+            sci_wrdata(3)=>serdes_sync_0_sci_wrdata(3),sci_wrdata(2)=>serdes_sync_0_sci_wrdata(2),
+            sci_wrdata(1)=>serdes_sync_0_sci_wrdata(1),sci_wrdata(0)=>serdes_sync_0_sci_wrdata(0),
+            tx_disp_sel(0)=>serdes_sync_0_tx_disp_sel(0),tx_force_disp(0)=>serdes_sync_0_tx_force_disp(0),
+            tx_k(0)=>serdes_sync_0_tx_k(0),txdata(7)=>serdes_sync_0_txdata(7),
+            txdata(6)=>serdes_sync_0_txdata(6),txdata(5)=>serdes_sync_0_txdata(5),
+            txdata(4)=>serdes_sync_0_txdata(4),txdata(3)=>serdes_sync_0_txdata(3),
+            txdata(2)=>serdes_sync_0_txdata(2),txdata(1)=>serdes_sync_0_txdata(1),
+            txdata(0)=>serdes_sync_0_txdata(0),cyawstn=>serdes_sync_0_cyawstn,
+            hdinn=>serdes_sync_0_hdinn,hdinp=>serdes_sync_0_hdinp,hdoutn=>serdes_sync_0_hdoutn,
+            hdoutp=>serdes_sync_0_hdoutp,lsm_status_s=>serdes_sync_0_lsm_status_s,
+            pll_lol=>serdes_sync_0_pll_lol,pll_refclki=>serdes_sync_0_pll_refclki,
+            rsl_disable=>serdes_sync_0_rsl_disable,rsl_rst=>serdes_sync_0_rsl_rst,
+            rsl_rx_rdy=>serdes_sync_0_rsl_rx_rdy,rsl_tx_rdy=>serdes_sync_0_rsl_tx_rdy,
+            rst_dual_c=>serdes_sync_0_rst_dual_c,rx_cdr_lol_s=>serdes_sync_0_rx_cdr_lol_s,
+            rx_los_low_s=>serdes_sync_0_rx_los_low_s,rx_pclk=>serdes_sync_0_rx_pclk,
+            rx_pcs_rst_c=>serdes_sync_0_rx_pcs_rst_c,rx_pwrup_c=>serdes_sync_0_rx_pwrup_c,
+            rx_serdes_rst_c=>serdes_sync_0_rx_serdes_rst_c,rxrefclk=>serdes_sync_0_rxrefclk,
+            sci_en=>serdes_sync_0_sci_en,sci_en_dual=>serdes_sync_0_sci_en_dual,
+            sci_int=>serdes_sync_0_sci_int,sci_rd=>serdes_sync_0_sci_rd,sci_sel=>serdes_sync_0_sci_sel,
+            sci_sel_dual=>serdes_sync_0_sci_sel_dual,sci_wrn=>serdes_sync_0_sci_wrn,
+            serdes_pdb=>serdes_sync_0_serdes_pdb,serdes_rst_dual_c=>serdes_sync_0_serdes_rst_dual_c,
+            signal_detect_c=>serdes_sync_0_signal_detect_c,sli_rst=>sli_rst_wire0,
+            tx_idle_c=>serdes_sync_0_tx_idle_c,tx_pclk=>serdes_sync_0_tx_pclk,
+            tx_pcs_rst_c=>serdes_sync_0_tx_pcs_rst_c,tx_pwrup_c=>serdes_sync_0_tx_pwrup_c,
+            tx_serdes_rst_c=>serdes_sync_0_tx_serdes_rst_c);
+    gnd <= '0' ;
+    
+end architecture pcs2_240; -- sbp_module=true 
+

media_interfaces/ecp5/240MHz/pcs_240.vhd

+
+
+--
+-- Verific VHDL Description of module pcs_240
+--
+
+library ieee ;
+use ieee.std_logic_1164.all ;
+
+entity pcs_240 is
+    port (serdes_sync_0_rx_cv_err: out std_logic_vector(0 downto 0);
+        serdes_sync_0_rx_disp_err: out std_logic_vector(0 downto 0);
+        serdes_sync_0_rx_k: out std_logic_vector(0 downto 0);
+        serdes_sync_0_rxdata: out std_logic_vector(7 downto 0);
+        serdes_sync_0_sci_addr: in std_logic_vector(5 downto 0);
+        serdes_sync_0_sci_rddata: out std_logic_vector(7 downto 0);
+        serdes_sync_0_sci_wrdata: in std_logic_vector(7 downto 0);
+        serdes_sync_0_tx_disp_sel: in std_logic_vector(0 downto 0);
+        serdes_sync_0_tx_force_disp: in std_logic_vector(0 downto 0);
+        serdes_sync_0_tx_k: in std_logic_vector(0 downto 0);
+        serdes_sync_0_txdata: in std_logic_vector(7 downto 0);
+        serdes_sync_0_cyawstn: in std_logic;
+        serdes_sync_0_hdinn: in std_logic;
+        serdes_sync_0_hdinp: in std_logic;
+        serdes_sync_0_hdoutn: out std_logic;
+        serdes_sync_0_hdoutp: out std_logic;
+        serdes_sync_0_lsm_status_s: out std_logic;
+        serdes_sync_0_pll_lol: out std_logic;
+        serdes_sync_0_pll_refclki: in std_logic;
+        serdes_sync_0_rsl_disable: in std_logic;
+        serdes_sync_0_rsl_rst: in std_logic;
+        serdes_sync_0_rsl_rx_rdy: out std_logic;
+        serdes_sync_0_rsl_tx_rdy: out std_logic;
+        serdes_sync_0_rst_dual_c: in std_logic;
+        serdes_sync_0_rx_cdr_lol_s: out std_logic;
+        serdes_sync_0_rx_los_low_s: out std_logic;
+        serdes_sync_0_rx_pclk: out std_logic;
+        serdes_sync_0_rx_pcs_rst_c: in std_logic;
+        serdes_sync_0_rx_pwrup_c: in std_logic;
+        serdes_sync_0_rx_serdes_rst_c: in std_logic;
+        serdes_sync_0_rxrefclk: in std_logic;
+        serdes_sync_0_sci_en: in std_logic;
+        serdes_sync_0_sci_en_dual: in std_logic;
+        serdes_sync_0_sci_int: out std_logic;
+        serdes_sync_0_sci_rd: in std_logic;
+        serdes_sync_0_sci_sel: in std_logic;
+        serdes_sync_0_sci_sel_dual: in std_logic;
+        serdes_sync_0_sci_wrn: in std_logic;
+        serdes_sync_0_serdes_pdb: in std_logic;
+        serdes_sync_0_serdes_rst_dual_c: in std_logic;
+        serdes_sync_0_signal_detect_c: in std_logic;
+        serdes_sync_0_tx_idle_c: in std_logic;
+        serdes_sync_0_tx_pclk: out std_logic;
+        serdes_sync_0_tx_pcs_rst_c: in std_logic;
+        serdes_sync_0_tx_pwrup_c: in std_logic;
+        serdes_sync_0_tx_serdes_rst_c: in std_logic
+    );
+    
+end entity pcs_240; -- sbp_module=true 
+
+architecture pcs_240 of pcs_240 is 
+    component serdes_sync_0 is
+        port (rx_cv_err: out std_logic_vector(0 downto 0);
+            rx_disp_err: out std_logic_vector(0 downto 0);
+            rx_k: out std_logic_vector(0 downto 0);
+            rxdata: out std_logic_vector(7 downto 0);
+            sci_addr: in std_logic_vector(5 downto 0);
+            sci_rddata: out std_logic_vector(7 downto 0);
+            sci_wrdata: in std_logic_vector(7 downto 0);
+            tx_disp_sel: in std_logic_vector(0 downto 0);
+            tx_force_disp: in std_logic_vector(0 downto 0);
+            tx_k: in std_logic_vector(0 downto 0);
+            txdata: in std_logic_vector(7 downto 0);
+            cyawstn: in std_logic;
+            hdinn: in std_logic;
+            hdinp: in std_logic;
+            hdoutn: out std_logic;
+            hdoutp: out std_logic;
+            lsm_status_s: out std_logic;
+            pll_lol: out std_logic;
+            pll_refclki: in std_logic;
+            rsl_disable: in std_logic;
+            rsl_rst: in std_logic;
+            rsl_rx_rdy: out std_logic;
+            rsl_tx_rdy: out std_logic;
+            rst_dual_c: in std_logic;
+            rx_cdr_lol_s: out std_logic;
+            rx_los_low_s: out std_logic;
+            rx_pclk: out std_logic;
+            rx_pcs_rst_c: in std_logic;
+            rx_pwrup_c: in std_logic;
+            rx_serdes_rst_c: in std_logic;
+            rxrefclk: in std_logic;
+            sci_en: in std_logic;
+            sci_en_dual: in std_logic;
+            sci_int: out std_logic;
+            sci_rd: in std_logic;
+            sci_sel: in std_logic;
+            sci_sel_dual: in std_logic;
+            sci_wrn: in std_logic;
+            serdes_pdb: in std_logic;
+            serdes_rst_dual_c: in std_logic;
+            signal_detect_c: in std_logic;
+            sli_rst: in std_logic;
+            tx_idle_c: in std_logic;
+            tx_pclk: out std_logic;
+            tx_pcs_rst_c: in std_logic;
+            tx_pwrup_c: in std_logic;
+            tx_serdes_rst_c: in std_logic
+        );
+        
+    end component serdes_sync_0; -- not_need_bbox=true 
+    
+    
+    signal sli_rst_wire0,gnd : std_logic; 
+begin
+    sli_rst_wire0 <= serdes_sync_0_serdes_rst_dual_c OR  serdes_sync_0_tx_serdes_rst_c OR  (NOT serdes_sync_0_serdes_pdb) OR  (NOT serdes_sync_0_tx_pwrup_c);
+    serdes_sync_0_inst: component serdes_sync_0 port map (rx_cv_err(0)=>serdes_sync_0_rx_cv_err(0),
+            rx_disp_err(0)=>serdes_sync_0_rx_disp_err(0),rx_k(0)=>serdes_sync_0_rx_k(0),
+            rxdata(7)=>serdes_sync_0_rxdata(7),rxdata(6)=>serdes_sync_0_rxdata(6),
+            rxdata(5)=>serdes_sync_0_rxdata(5),rxdata(4)=>serdes_sync_0_rxdata(4),
+            rxdata(3)=>serdes_sync_0_rxdata(3),rxdata(2)=>serdes_sync_0_rxdata(2),
+            rxdata(1)=>serdes_sync_0_rxdata(1),rxdata(0)=>serdes_sync_0_rxdata(0),
+            sci_addr(5)=>serdes_sync_0_sci_addr(5),sci_addr(4)=>serdes_sync_0_sci_addr(4),
+            sci_addr(3)=>serdes_sync_0_sci_addr(3),sci_addr(2)=>serdes_sync_0_sci_addr(2),
+            sci_addr(1)=>serdes_sync_0_sci_addr(1),sci_addr(0)=>serdes_sync_0_sci_addr(0),
+            sci_rddata(7)=>serdes_sync_0_sci_rddata(7),sci_rddata(6)=>serdes_sync_0_sci_rddata(6),
+            sci_rddata(5)=>serdes_sync_0_sci_rddata(5),sci_rddata(4)=>serdes_sync_0_sci_rddata(4),
+            sci_rddata(3)=>serdes_sync_0_sci_rddata(3),sci_rddata(2)=>serdes_sync_0_sci_rddata(2),
+            sci_rddata(1)=>serdes_sync_0_sci_rddata(1),sci_rddata(0)=>serdes_sync_0_sci_rddata(0),
+            sci_wrdata(7)=>serdes_sync_0_sci_wrdata(7),sci_wrdata(6)=>serdes_sync_0_sci_wrdata(6),
+            sci_wrdata(5)=>serdes_sync_0_sci_wrdata(5),sci_wrdata(4)=>serdes_sync_0_sci_wrdata(4),
+            sci_wrdata(3)=>serdes_sync_0_sci_wrdata(3),sci_wrdata(2)=>serdes_sync_0_sci_wrdata(2),
+            sci_wrdata(1)=>serdes_sync_0_sci_wrdata(1),sci_wrdata(0)=>serdes_sync_0_sci_wrdata(0),
+            tx_disp_sel(0)=>serdes_sync_0_tx_disp_sel(0),tx_force_disp(0)=>serdes_sync_0_tx_force_disp(0),
+            tx_k(0)=>serdes_sync_0_tx_k(0),txdata(7)=>serdes_sync_0_txdata(7),
+            txdata(6)=>serdes_sync_0_txdata(6),txdata(5)=>serdes_sync_0_txdata(5),
+            txdata(4)=>serdes_sync_0_txdata(4),txdata(3)=>serdes_sync_0_txdata(3),
+            txdata(2)=>serdes_sync_0_txdata(2),txdata(1)=>serdes_sync_0_txdata(1),
+            txdata(0)=>serdes_sync_0_txdata(0),cyawstn=>serdes_sync_0_cyawstn,
+            hdinn=>serdes_sync_0_hdinn,hdinp=>serdes_sync_0_hdinp,hdoutn=>serdes_sync_0_hdoutn,
+            hdoutp=>serdes_sync_0_hdoutp,lsm_status_s=>serdes_sync_0_lsm_status_s,
+            pll_lol=>serdes_sync_0_pll_lol,pll_refclki=>serdes_sync_0_pll_refclki,
+            rsl_disable=>serdes_sync_0_rsl_disable,rsl_rst=>serdes_sync_0_rsl_rst,
+            rsl_rx_rdy=>serdes_sync_0_rsl_rx_rdy,rsl_tx_rdy=>serdes_sync_0_rsl_tx_rdy,
+            rst_dual_c=>serdes_sync_0_rst_dual_c,rx_cdr_lol_s=>serdes_sync_0_rx_cdr_lol_s,
+            rx_los_low_s=>serdes_sync_0_rx_los_low_s,rx_pclk=>serdes_sync_0_rx_pclk,
+            rx_pcs_rst_c=>serdes_sync_0_rx_pcs_rst_c,rx_pwrup_c=>serdes_sync_0_rx_pwrup_c,
+            rx_serdes_rst_c=>serdes_sync_0_rx_serdes_rst_c,rxrefclk=>serdes_sync_0_rxrefclk,
+            sci_en=>serdes_sync_0_sci_en,sci_en_dual=>serdes_sync_0_sci_en_dual,
+            sci_int=>serdes_sync_0_sci_int,sci_rd=>serdes_sync_0_sci_rd,sci_sel=>serdes_sync_0_sci_sel,
+            sci_sel_dual=>serdes_sync_0_sci_sel_dual,sci_wrn=>serdes_sync_0_sci_wrn,
+            serdes_pdb=>serdes_sync_0_serdes_pdb,serdes_rst_dual_c=>serdes_sync_0_serdes_rst_dual_c,
+            signal_detect_c=>serdes_sync_0_signal_detect_c,sli_rst=>sli_rst_wire0,
+            tx_idle_c=>serdes_sync_0_tx_idle_c,tx_pclk=>serdes_sync_0_tx_pclk,
+            tx_pcs_rst_c=>serdes_sync_0_tx_pcs_rst_c,tx_pwrup_c=>serdes_sync_0_tx_pwrup_c,
+            tx_serdes_rst_c=>serdes_sync_0_tx_serdes_rst_c);
+    gnd <= '0' ;
+    
+end architecture pcs_240; -- sbp_module=true 
+