Added status register, not yet tested in hardware

media_interfaces/sync/med_sync_control.vhd

@@ -312,7 +312,8 @@ PROC_REG : process begin
           BUS_TX.data <= x"10000000";
         end if;
       when "01"   => BUS_TX.data <= request_retr_counter & start_retr_counter;
-      --when "11"   => BUS_TX.data <= x"000000" & DEBUG_RX_CONTROL_i(31 downto 24);
+      when "10"   => BUS_TX.data <= STAT_RX_CONTROL_i(15 downto 0) & STAT_TX_CONTROL_i(15 downto 0);
+      when "11"   => BUS_TX.data <= STAT_RESET;  
       when others => BUS_TX.unknown <= '1';
     end case;
   end if;

media_interfaces/sync/rx_control.vhd

@@ -684,20 +684,27 @@ MAKE_RESET_OUT         <= make_reset_i when rising_edge(CLK_200);
 ----------------------------------------------------------------------
 -- Debug and Status
 ---------------------------------------------------------------------- 
-STAT_REG_OUT(3 downto 0)   <= rx_state_bits;
-STAT_REG_OUT(4)            <= got_link_ready_i;
-STAT_REG_OUT(5)            <= ct_fifo_afull;
-STAT_REG_OUT(6)            <= ct_fifo_empty;
-STAT_REG_OUT(7)            <= ct_fifo_write;
-STAT_REG_OUT(15 downto 8)  <= reg_rx_data_in when rising_edge(clk_100); --rx_data(7 downto 0);
-STAT_REG_OUT(16)           <= rx_data(16);
-STAT_REG_OUT(17)           <= use_crc;
-STAT_REG_OUT(18)           <= reset_retrans;
-STAT_REG_OUT(19)           <= load_use_crc;
---STAT_REG_OUT(31 downto 18) <= (others => '0');
-STAT_REG_OUT(23 downto 20) <= (others => '0');
-STAT_REG_OUT(31 downto 24) <= good_pos_counter;
-
+process(CLK_100)
+begin
+  if rising_edge(CLK_100) then
+    STAT_REG_OUT <= (others => '0');
+        
+    STAT_REG_OUT(3 downto 0)   <= rx_state_bits;
+    STAT_REG_OUT(4)            <= got_link_ready_i;
+    STAT_REG_OUT(5)            <= ct_fifo_afull;
+    STAT_REG_OUT(6)            <= ct_fifo_empty;
+    STAT_REG_OUT(7)            <= ct_fifo_write;
+    STAT_REG_OUT(15 downto 8)  <= reg_rx_data_in; --rx_data(7 downto 0);
+--
+    STAT_REG_OUT(16)           <= rx_data(16);
+    STAT_REG_OUT(17)           <= use_crc;
+    STAT_REG_OUT(18)           <= reset_retrans;
+    STAT_REG_OUT(19)           <= load_use_crc;
+
+    STAT_REG_OUT(23 downto 20) <= (others => '0');
+    STAT_REG_OUT(31 downto 24) <= good_pos_counter;
+  end if;
+end process;
 
 DEBUG_OUT(3 downto 0)   <= rx_state_bits;
 DEBUG_OUT(4)            <= got_link_ready_i;

media_interfaces/sync/tx_control.vhd

@@ -566,34 +566,34 @@ begin
 --  DEBUG_OUT(23 downto 16) <= tx_data_200(7 downto 0);
 --  DEBUG_OUT(31 downto 24) <= ram_dout(7 downto 0);
 --  DEBUG_OUT(31 downto 24) <= send_chksum_counter;
-
     
   process(CLK_100)
     begin
       if rising_edge(CLK_100) then
         STAT_REG_OUT <= (others => '0');
---         STAT_REG_OUT(7 downto 0)   <= std_logic_vector(ram_fill_level);
+
         STAT_REG_OUT(3 downto 0)   <= state_bits;
+        STAT_REG_OUT(4)           <= RESET_IN;
+        STAT_REG_OUT(5)           <= ct_fifo_afull;
+        STAT_REG_OUT(6)           <= ct_fifo_read;
+        STAT_REG_OUT(7)           <= ct_fifo_write;
         
+        STAT_REG_OUT(8)            <= ram_empty;
+        STAT_REG_OUT(9)            <= tx_allow_qtx;
+        STAT_REG_OUT(10)           <= TX_ALLOW_IN;
+        STAT_REG_OUT(11)           <= load_eop;
+        STAT_REG_OUT(12)           <= send_dlm_i;
+       
+        STAT_REG_OUT(13)           <= make_restart_i;
+        STAT_REG_OUT(14)           <= make_request_i;
+        STAT_REG_OUT(15)           <= load_read_pointer_i;
+
+        --         STAT_REG_OUT(7 downto 0)   <= std_logic_vector(ram_fill_level);
 --         STAT_REG_OUT(7)   <= TX_K_OUT;
 --         STAT_REG_OUT(15 downto 8) <= TX_DATA_OUT;
-        STAT_REG_OUT(15 downto 8)  <= std_logic_vector(ram_read_addr);
+--        STAT_REG_OUT(15 downto 8)  <= std_logic_vector(ram_read_addr);
+--
 --         STAT_REG_OUT(16)           <= ram_afull;
-        STAT_REG_OUT(17)           <= ram_empty;
-        STAT_REG_OUT(18)           <= tx_allow_qtx;
-        STAT_REG_OUT(19)           <= TX_ALLOW_IN;
-        STAT_REG_OUT(20)           <= make_restart_i;
-        STAT_REG_OUT(21)           <= make_request_i;
-        STAT_REG_OUT(22)           <= load_eop;
-        STAT_REG_OUT(23)           <= send_dlm_i;
-        STAT_REG_OUT(24)           <= make_restart_i;
-        STAT_REG_OUT(25)           <= make_request_i;
-        STAT_REG_OUT(26)           <= load_read_pointer_i;
-        STAT_REG_OUT(27)           <= ct_fifo_afull;
-        STAT_REG_OUT(28)           <= ct_fifo_read;
-        STAT_REG_OUT(29)           <= ct_fifo_write;
-        STAT_REG_OUT(30)           <= RESET_IN;
-        STAT_REG_OUT(31)           <= '0';
 --         STAT_REG_OUT(31 downto 27) <= (others => '0');
       end if;
     end process;