dirich5s1 new reset routine and more stable CDR settings, mt (332a0d96) · Commits · DAQ / Externals / TRB / trbnet · GitLab

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332a0d96

Commit 332a0d96 authored 2 years ago by HADES DAQ

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dirich5s1 new reset routine and more stable CDR settings, mt

parent 6271736c

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Changes 6

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media_interfaces/ecp5/chan0_0/serdes_sync_0.ipx 0 additions, 7 deletions

media_interfaces/ecp5/chan0_0/serdes_sync_0.ipx
media_interfaces/ecp5/chan0_0/serdes_sync_0.lpc 16 additions, 16 deletions

media_interfaces/ecp5/chan0_0/serdes_sync_0.lpc
media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd 37 additions, 37 deletions

media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd
media_interfaces/med_ecp5_sfp_sync.vhd 10 additions, 6 deletions

media_interfaces/med_ecp5_sfp_sync.vhd
media_interfaces/sync/med_sync_control.vhd 62 additions, 25 deletions

media_interfaces/sync/med_sync_control.vhd
media_interfaces/sync/med_sync_define.vhd 29 additions, 0 deletions

media_interfaces/sync/med_sync_define.vhd

with 154 additions and 91 deletions

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