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padiwa
Commits
c6d71fbb
Commit
c6d71fbb
authored
6 years ago
by
Jan Michel
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fix syntax for LEDs in padiwa amps 2
parent
aab056ff
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amps2/padiwa_amps2.vhd
+5
-5
5 additions, 5 deletions
amps2/padiwa_amps2.vhd
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5 deletions
amps2/padiwa_amps2.vhd
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View file @
c6d71fbb
...
...
@@ -362,7 +362,7 @@ THE_PWM_GEN : entity work.pwm_generator
-- wait until rising_edge(clk_i);
wait
until
rising_edge
(
clk_66
);
for
i
in
1
to
8
loop
if
(
last_inp
((
i
-1
)
*
2
)
xor
inp_status
((
i
-1
)
*
2
)
=
'1'
and
(
led_timer
(
i
)(
23
downto
21
)
>
0
)
then
if
(
last_inp
((
i
-1
)
*
2
)
xor
inp_status
((
i
-1
)
*
2
)
)
=
'1'
and
(
led_timer
(
i
)(
23
downto
21
)
>
0
)
then
led_state
(
i
)
<=
not
led_state
(
i
);
led_timer
(
i
)
<=
0
;
elsif
led_timer
(
i
)(
23
)
=
'1'
then
...
...
@@ -374,7 +374,7 @@ THE_PWM_GEN : entity work.pwm_generator
end
process
;
gen_leds
:
for
i
in
1
to
8
generate
LED
(
i
)
<=
not
led
s
((
i
-1
)
*
2
)
when
led_status
(
8
)
=
'1'
else
not
led_status
(
i
-1
);
LED
(
i
)
<=
not
led
_state
(
i
)
when
led_status
(
8
)
=
'1'
else
not
led_status
(
i
-1
);
end
generate
;
...
...
@@ -453,9 +453,9 @@ last_inp_long_reg <= inp_long_reg when rising_edge(clk_i);
-- Test Output
---------------------------------------------------------------------------
--TEST_LINE(7 downto 0) <= selected_delay;
TEST_LINE
(
13
)
<=
SPI_CLK
;
TEST_LINE
(
12
)
<=
SPI_out
;
TEST_LINE
(
11
)
<=
SPI_in
;
--
TEST_LINE(13) <= SPI_CLK;
--
TEST_LINE(12) <= SPI_out;
--
TEST_LINE(11) <= SPI_in;
TEST_LINE
(
10
downto
8
)
<=
(
others
=>
'0'
);
end
architecture
;
...
...
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