OHWR General cores

General cores is a library of widely used cores but still small enough not to require a dedicated repository.

In modules/common there are general purpose cores:

• The package gencores_pkg provides the declarations of the components (this is not required, you can always directly instantiate the entities) but also some useful subprograms like functions for gray encode/decode, boolean conversions...

• The package matrix_pkg declares a 2d array of std_logic, and some subprograms to handle it.

• For clock-domain crossing or asynchronous signal register, use gc_sync_ffs. It also has an edge detector. The other synchronizer gc_sync_register is deprecated. It can synchronize multiple signals at the same time but doesn't ensure coherency between these signals.

  To pass words from one clock domain to another, you can use the module gc_sync_word_wr for writing data, and gc_sync_word_rd for reading data.

  To pass one pulse from one domain to another, use module gc_pulse_synchronizer or the version with resets gc_pulse_synchronizer2

  Module gc_async_signals_input_stage contains a complex handling for asynchronous signals (crossing clock domains, deglitcher, edge detection, pulse extension...)

• For reset generation, you can use gc_reset which generate synchronous resets once all the PLL lock signals are set. The module gc_reset_multi_aasd generate asynchronously asserted synchronously deasserted resets for multiple clock domains.

  The module gc_single_reset_gen is convenient to generate a single reset from multiple sources (like powerup signal and a reset button).

• Words can be packed or unpacked using the module gc_word_packer

• Module gc_i2c_slave provides a simple i2c slave. This module is used in gc_sfp_i2c_adapter to emulate an SFP DDM.

• The module gc_serial_dac provides an interface to a serial DAC.

• The module gc_rr_arbiter provides a round-robin arbiter amount an arbitrary number of requests. Similarly gc_arbitrated_mux provides a multiple channel tim-division multiplexr with round robin arbitration.

• The module gc_prio_encoder provides a combinational priority encoder.

• Module gc_bicolor_led_ctrl controls multiple bicolor leds, including the intensity.

• Module gc_big_adder provides a pipelined adder for wide numbers.

• Module gc_comparator provides a comparator with hysteresis.

• Module gc_moving_average compute the average of values over a sliding window. The size of the window is a power of 2.

• Module gc_crc_gen provides a generic parallel implementation of crc generator or checker.

• Module gc_dec_8b10b is an 8-bit to 10-bit decoder.

• Module gc_delay_gen is a delay line based on a pipeline, while module gc_delay_line implementation is based on a dual port RAM and provides a valid signal.

• Module gc_ds182x_readout provides a one-wire interface for temperature and unique id DS182X chips. It replaces the deprecated gc_ds182x_interface

• Module gc_dual_pi_controller is a two channels, proportional integral (PI) controller.

• To extend a pulse, several modules are provided:

  • gc_dyn_extend_pulse has an input for the length.
  • gc_extend_pulse has a fixed length.

• To deglitch a signal:

  • gc_dyn_glitch_filt accepts the minimum length as an input.
  • gc_glitch_filt is static: the length is provided as a parameter.

• Module gc_fsm_watchdog provides a simple watchdog.

• To mesure a frequency:

  • gc_frequency_meter provides a single channel counter.
  • gc_multichannel_frequency_meter is an optimized version for multiple channels.

In modules/genrams there are fifo and ram cores:

The convention is to use generic_xxx modules whose implementation may depend on the target.

• The package genram_pkg declares ram types, utility functions and the components.

• The package memory_loader_pkg declares functions that reads data from a file. They are useful to initialize the rams (and can be used for synthesis).

• The module generic_spram available for altera and for xilinx is a simple port synchronous ram.

• The module generic_simple_dpram available for altera and for xilinx is a dual port, dual clock, synchronous ram. The port A is write-only, the port B is read-only.

• The module generic_dpram available for altera and for xilinx is a dual port, dual clock, synchronous ram. Both ports are read/write.

• The module generic_dpram_mixed available for altera is a dual port, dual clock, synchronous ram. Both ports are read/write, and the size of the ports can be different.

• The module generic_sync_fifo is a synchronous fifo, with multiple flags available.

• The module generic_async_fifo is also a fifo with multiple flags available, but with different clocks for inputs and outputs.

• The module generic_async_fifo_dual_rst is also a fifo with multiple flags available, but with different clocks for inputs and outputs and with a reset input for each clock domain.

• The module generic_shiftreg_fifo is a synchronous fifo based on shift registers.

Directory modules/wishbone contains modules for wishbone.

• The package wishbone_pkg declare the records for the wishbone bus and some utilities.

• There are several peripherals:

  • wb_dma is a dma controller.
  • wb_dpram is a dual port ram controlled by two wishbone buses.
  • wb_gpio_port is a gpio controller.
  • wb_i2c_bridge is an i2c slave to wishbone master.
  • [wb_i2c_master]](modules/wishbone/wb_i2c_master) is an i2c master.
  • wb_irq contains irq controllers and generators.
  • wb_onewire_master is a onewire master.
  • wb_serial_lcd is an lcd controller.
  • wb_simple_pwm is a pwm controller supporting up to 8 channels.
  • wb_simple_timer is a simple counter.
  • wb_spi is an spi controller
  • wb_spi_flash is an spi flash controller
  • wb_uart is an uart.
  • wb_vic is the vectored interrupt controller.
  • wb_ds182x_readout is a direct interface to the digital thermometer.

• There are utilities to handle a wishbone bus:

  • wb_clock_crossing handle clock domain crossing.
  • wb_register add a pipeline register.

• There are modules to convert to a different bus

  • wb_async_bridge is a bridge with the AT91SAM9x CPU external bus interface.
  • wb_axi4lite_bridge is an axi4lite to wishbone bridge

• There a modules to build a bus hierarchy:

  • wb_bus_fanout is a simple master to multiple slave decoder.
  • wb_crossbar is a generic multiple masters and multiple slaves crossbar.
  • wb_split is a very simple crossbar for 1 master and 2 slaves.
  • wb_remapper allows to remap addresses.
  • wb_conmax is an interconnect matrix, superseeded by the crossbar.
  • wb_metadata is a little helper to create metadata for the convention.