- Jul 19, 2019
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Tristan Gingold authored
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- Jun 17, 2019
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Tristan Gingold authored
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- Jun 08, 2018
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Dimitris Lampridis authored
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- Mar 19, 2018
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Dimitris Lampridis authored
For the few peripherals where it was being used (eg. uart, spi, etc) the output port has been renamed to "int_o". The only peripheral that was not touched is "wb_eic.vhd", because this one is being used by wbgen, and it would require users to update their wbgen tool as well. So, until a new tool is introduced, wbgen-generated interrupt controllers will have an output port called wb_int_o".
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- Dec 13, 2017
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Grzegorz Daniluk authored
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- Sep 27, 2016
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Tomasz Włostowski authored
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- Jun 24, 2013
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Tomasz Włostowski authored
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- Mar 08, 2013
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Tomasz Włostowski authored
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- Feb 14, 2013
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Wesley W. Terpstra authored
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- Oct 02, 2012
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Tomasz Włostowski authored
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- Mar 28, 2012
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Tomasz Włostowski authored
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Tomasz Wlostowski authored
Added: - asynchronous SRAM bus -> Wishbone bridge (wb_async_bridge) - Conmax interconnect (wb_conmax) - GPIO port (wb_gpio_port) - Very simple timer (wb_simple timer) - Simple UART (wb_uart) - Vectored Interrupt controller (wb_vic) - Virtual UART (mmapped FIFO, wb_virtual_uart) - wbgen2 core generator libraries (wbgen2)
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- Jan 16, 2012
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Tomasz Włostowski authored
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- May 02, 2011
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Tomasz Wlostowski authored
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