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Adrian A. Weber a.weber
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Adrian Byszuk
a.byszuk
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Benedikt Gutsche b.gutsche
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Claudiu Schiaua schiaua_AT_nipne.ro
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David Emschermann
d.emschermann
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David Schledt
dschledt
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Dirk Hutter d.hutter
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Dmitry Finogeev d.finogeev
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Erik Goldenstein e.goldenstein
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Esteban Rubio
rubio_AT_physi.uni-heidelberg.de
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Falk Zorn f.zorn
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Ingo Froehlich
i.froehlich
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Jan de Cuveland j.decuveland
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Jan Michel j.michel
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Jochen Fruehauf j.fruehauf
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Joerg Lehnert j.lehnert
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Jogender Saini j.saini
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Khaled Ismail k.ismail
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Marek Guminski mguminski
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Michal Kruszewski mkruszew_AT_mion.elka.pw.edu.pl
- Jan 28, 2021
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Wojciech M. Zabolotny authored
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Wojciech M. Zabolotny authored
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- Dec 30, 2020
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Marek Guminski authored
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- Oct 29, 2020
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Marek Guminski authored
It is rewritten in VHDL (by qermit) It supports SDIO It it can send up to 160 bits (original could send 128)
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- Oct 02, 2020
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Marek Guminski authored
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Marek Guminski authored
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- Jul 13, 2020
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Marek Guminski authored
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Marek Guminski authored
We don't have necessary runners on CBM repository.
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Marek Guminski authored
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Marek Guminski authored
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Marek Guminski authored
Scoped constrains are included.
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Marek Guminski authored
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- Mar 26, 2020
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Dimitris Lampridis authored
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Dimitris Lampridis authored
Signed-off-by:Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
Using the guidelines from here: https://gitlab.cern.ch/be-co-ht-documents/project-management-guidelines/-/blob/master/how-to-write-changelog.rst Signed-off-by:
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Tristan Gingold authored
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Tristan Gingold authored
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- Mar 17, 2020
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Federico Vaga authored
Instead of check for version here and there, the main code always uses the latest API, and in a preprocessor ``if`` statement I implemented the compatibility layer. Like this it will be easier to apply patches from the kernel to our local driver Signed-off-by:Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
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- Mar 13, 2020
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Federico Vaga authored
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Federico Vaga authored
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Federico Vaga authored
sw: Update spi-ocores See merge request project/general-cores!3
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- Mar 11, 2020
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Tristan Gingold authored
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- Mar 06, 2020
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Dimitris Lampridis authored
Signed-off-by: -
Dimitris Lampridis authored
Signed-off-by: -
Dimitris Lampridis authored
Also perform cleanup of sync and edge modules. Signed-off-by: -
Tomasz Włostowski authored
Signed-off-by:
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- Mar 05, 2020
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Tristan Gingold authored
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Dimitris Lampridis authored
Signed-off-by: -
Dimitris Lampridis authored
Reported by Olof Olof Kindgren (@olofk). See also merge request !4. Signed-off-by: -
Dimitris Lampridis authored
This allows them to be used right after in component declarations. Signed-off-by: -
Dimitris Lampridis authored
This is especially beneficial when trying to meet timing in the GN4124 core (on Spartan6), where the async FIFOs are clocked on one side at 200MHz. Apparently, the KEEP_HIERARCHY attribute makes it much easier for ISE 14.7 to reach timing closure. It also helps in general to ensure that the synchronisation structures remain intact and do not get merged in unpredictable ways with other parts of the design. Signed-off-by: -
Dimitris Lampridis authored
Signed-off-by:
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- Mar 04, 2020
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Tristan Gingold authored
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- Mar 03, 2020
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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- Feb 25, 2020
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Mamta Shukla authored
Align polarity and phase for SPI_OCORES_CTRL_Tx_NEG and SPI_OCORES_CTRL_Rx_NEG with check for SPI_CPHA and mode(CPOL). Signed-off-by:Mamta Shukla <mamta.ramendra.shukla@cern.ch>
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Mamta Shukla authored
Signed-off-by:
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- Feb 19, 2020
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Christos Gentsos authored
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