Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Without this option, the two outputs of the module are in different clock domains. The frequency value is in the clk_in domain, while the "valid" flag is in the system clock domain.

With the new option, if set to TRUE, both outputs will be in the system clock domain.

This commit does three changes to gc_sync_word_wr:

1. It converts it to use internally gc_pulse_synchroniser2
2. It introduces a new "busy" output bit
3. It introduces a new generic, g_AUTO_WR which instructs the core to write a new word continously, without input from the user.

When trying to compile for nanoXplore synthesis fails, complaining
about those signals -- although they're unused.

This is needed for fixed-latency streamers. Module was written by Tom,
he added it to wr-cores whereas it belongs here, I've moved it.

This is beneficial because the gc_sync_ffs has a Xilinx "keep" attribute, which prevents the tools
from trimming out unused logic, even when the user has set the relevant generics to "FALSE".