For the few peripherals where it was being used (eg. uart, spi, etc) the output port
has been renamed to "int_o".

The only peripheral that was not touched is "wb_eic.vhd", because this one is being used
by wbgen, and it would require users to update their wbgen tool as well. So, until a new
tool is introduced, wbgen-generated interrupt controllers will have an output port called
wb_int_o".

PCIe must respond to reads within a fairly tight deadline.
If we allow too many enqueued operations, that deadline may be missed.
Using a smaller FIFO depth causes back-pressure on the PCIe bus, slowing the
request arrival rate and thus increasing the time a single WB op can take.

Concretely, this makes it possible to perform an SPI flash write within
the PCIe time limit.

This is done to better reflect the interface of the module (structured Wishbone).
The documentation of the module is also changed in this respect.

Using the volatile configuration register to configure a flash chip
is a bad idea. The problem is that if the FPGA is reset, the flash
may be in a state inconsistent with what the FPGA requires to boot.

The correct solution is to configure the non-volatile configuration
register on the chip to what the FPGA expects on power-on. Then use
these same settings inside the flash core.

Going this route makes it necessary for software to be able to set
the non-volatile configuration register. Rather than making the core
even more complicated than it is, I have elected to add a FIFO which
software can fill to issue custom SPI commands. Since erase can only
be done from software anyway, I removed this code and let erase use
the custom command FIFO.

Also updated the rest of the documentation file to have a pretty
regmap.

Signed-off-by: Theodor Stana <t.stana@cern.ch>

- an FSM watchdog component was added to the multiboot_fsm; the timeout of
the wathcdog is reflected in the component's status register
- multiboot_regs was wbgen-ized
- updated wb_xil_multiboot top-level to reflect new changes

Signed-off-by: Theodor Stana <t.stana@cern.ch>
Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch>

- gc_i2c_slave     -- generic I2C slave to be used with a processor or tied to a
                      Wishbone interface
- gc_glitch_filter -- glitch filter with selectable number of taps
- wb_i2c_bridge    -- I2C bridge implementing the protocol defined with ELMA
                      for monitoring VME crates
- wb_xil_multiboot -- module that accesses the Spartan-6 configuration logic
                      for reconfiguring the FPGA using MultiBoot

Doc files for each of these modules can be found in the doc/ folder.

Signed-off-by: Theodor Stana <t.stana@cern.ch>
Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch>

Changes to the TCL scripts were needed.
To simplify future changes, the work was handed off to a shared function.

On slow Wishbone slave devices (eg. flash), the next request might
be decoded by the PHY before first has exited the read_first state.
In this case, the bar could change causing the mux to prematurely
lower the stall line.