doc/Makefile

doc/drawings/vic_state.eps

doc/drawings/vic_state.pdf

doc/fixinfo

doc/general-cores.in

doc/infofilter

doc/wb_gpio_port_regs.in

doc/wb_vic_regs.in

modules/common/Manifest.py

modules/common/gc_big_adder.vhd

modules/common/gc_crc_gen.vhd

modules/common/gc_extend_pulse.vhd

modules/common/gc_prio_encoder.vhd

modules/common/gc_pulse_synchronizer2.vhd

modules/common/gc_rr_arbiter.vhd

modules/common/gc_sync_ffs.vhd

modules/common/gc_word_packer.vhd

modules/common/gencores_pkg.vhd

modules/genrams/Manifest.py

modules/genrams/altera/Manifest.py