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Update to prepare the core for TFCv2

Vladimir Sidorenko requested to merge devel_vs into master
  • Added rx_headerflag to AGWB interface for Rx word alignment
  • Moved Rx/Tx latency optimisation configuration to generics
  • Added latch_rxdata_sp process in gbt_fpga_common.vhd to relax timing requirements
  • Updated IP cores to Vivado 2021.2

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