Optional creation of Test Registers by AGWB
Having build-in test features is essential for verification. Looking at the CBM CRI Wishbone complex we
- have a
test register
and ascratch DRAM
in thezeropage
- and hopefully will have a
test device
, see daq/fpga-firmware/cri/coordination#55
The first allows low level
testing, is very valuable for basic PCIe level testing, but since in zeropage
, this doesn't test the Wishbone bridge.
The second is targeted at CRI system level
testing, the focus is more on the whole gymnastics of DCA object creation, functional tests of the alarm system and the like.
What is missing in-between are simple tests to verify the Wishbone bridge logic, the response on ERR
and and especially TIMEOUT
. All one needs for this is
- an address which is write and readable
- an address which is write-only (and ERR's on read)
- an address which is read-only (and ERR's on write)
- an address which times-out (thus asserts neither
ack
norerr
)
I think the best place is to add this to the top
instance. Of course optionally, so that depending on application this can be enabled, or not.
The top.vhd
generated for the current cri-base
creates a cross bar defined by
constant c_address : t_wishbone_address_array(0 to 3-1) := (
0=>"00000000000000000111111111110000",
1=>"00000000000000000111111111101100",
2=>"00000000000000000100000000000000");
constant c_mask : t_wishbone_address_array(0 to 3-1) := (
0=>"00000000000000000111111111110000",
1=>"00000000000000000111111111111100",
2=>"00000000000000000111111111111110");
and a process which returns ID and VER for the whole design
-- Internal WB declaration
signal int_regs_wb_m_o : t_wishbone_master_out;
signal int_regs_wb_m_i : t_wishbone_master_in;
...
case int_addr is
when "0" =>
int_regs_wb_m_i.dat <= x"1ed91fca"; -- ID = crc32("top)
int_regs_wb_m_i.ack <= '1';
int_regs_wb_m_i.err <= '0';
when "1" =>
int_regs_wb_m_i.dat <= x"d4880d94"; -- VER
int_regs_wb_m_i.ack <= '1';
int_regs_wb_m_i.err <= '0';
when others =>
int_regs_wb_m_i.dat <= x"A5A5A5A5";
int_regs_wb_m_i.ack <= '0';
int_regs_wb_m_i.err <= '1';
end case;
...
wb_m_i(2) <= int_regs_wb_m_i;
It seems quite straight forward to implement AGWB
option(!), which
- will use a 3 bit rather than a 1 bit address sub-space of
int_regs
- decode the addresses
- "000" : returns
ID
as before - "001" : returns
VER
as before - "100" : implements a write/read register
- "101" : implements a write-only register,
ERR
on read - "110" : implements a read-only register.
ERR
on write, returns what was written into "101" - "111" : does nothing, neither
ack
orerr
are asserted, will timeout
- "000" : returns
- the addresses "010" and "011" are handled via
others
and returnERR
This would add a bus self-test feature, which is at a fixed address (defined by reserved
which is the same for all CRI designs).
With this we would have full test coverage:
- zeropage the
test register
andscratch DRAM
for low level PCIe tests - the above described addresses for Wishbone Bridge verification
- the
test device
described in daq/fpga-firmware/cri/coordination#55 for system level testing
Of relevance for @w.zabolotny_AT_elka.pw.edu.pl , @mkruszew_AT_mion.elka.pw.edu.pl , @mguminski , @i.froehlich