Merge branch 'cdc_workaround' into 'master'

Added a temporary solution for issue #2

See merge request daq/externals/gbt-fpga-cbm!5

cbm/gbt_fpga_common.vhd

@@ -253,6 +253,14 @@ architecture structural of gbt_fpga_common is
 
   --=====================================================================================--      
   
+  -- Temporary signals to address the issue https://git.cbm.gsi.de/daq/externals/gbt-fpga-cbm/-/issues/2
+  signal mgt_rx_headerflag_sync : std_logic_vector(1 to NUM_LINKS);
+  signal mgt_rx_header_locked_sync : std_logic_vector(1 to NUM_LINKS);
+  signal gbtbank_gbtrx_ready_sync : std_logic_vector(1 to NUM_LINKS);
+  signal s_tx_aligned_sync : std_logic_vector(1 to NUM_LINKS);
+  signal s_tx_aligned_val_sync : std_logic_vector(1 to NUM_LINKS);
+  signal s_link_ready_sync : std_logic_vector(1 to NUM_LINKS);
+
 --=================================================================================================--
 begin --========####   Architecture Body   ####========-- 
       --=================================================================================================--
@@ -745,15 +753,63 @@ begin --========####   Architecture Body   ####========--
       clk_sys_i               => frame_clk_i
     );
 
-    link_statuses(i).rx_headerflag(0)    <= mgt_rx_headerflag_s(i);
-    link_statuses(i).rx_header_locked(0) <= mgt_rx_header_locked_s(i);
-    link_statuses(i).rx_ready(0)         <= gbtbank_gbtrx_ready_s(i);
-    link_statuses(i).tx_phaligned(0)     <= s_tx_aligned(i);
-    link_statuses(i).tx_phaligned_val(0) <= s_tx_aligned_val(i);
+    link_statuses(i).rx_headerflag(0)    <= mgt_rx_headerflag_sync(i);
+    link_statuses(i).rx_header_locked(0) <= mgt_rx_header_locked_sync(i);
+    link_statuses(i).rx_ready(0)         <= gbtbank_gbtrx_ready_sync(i);
+    link_statuses(i).tx_phaligned(0)     <= s_tx_aligned_sync(i);
+    link_statuses(i).tx_phaligned_val(0) <= s_tx_aligned_val_sync(i);
     link_statuses(i).tx_ready(0)         <= s_tx_ready(i);
-    link_statuses(i).link_ready(0)       <= s_link_ready(i);
+    link_statuses(i).link_ready(0)       <= s_link_ready_sync(i);
     link_statuses(i).rx_ic_inactive(0)   <= ic_inactive(i);
     
+    sync_mgt_rx_headerflag_inst : entity general_cores.gc_sync
+    port map (
+      clk_i     => frame_clk_i,
+      rst_n_a_i => '1',
+      d_i       => mgt_rx_headerflag_s(i),
+      q_o       => mgt_rx_headerflag_sync(i)
+    );
+    
+    sync_mgt_rx_header_locked_inst : entity general_cores.gc_sync
+    port map (
+      clk_i     => frame_clk_i,
+      rst_n_a_i => '1',
+      d_i       => mgt_rx_header_locked_s(i),
+      q_o       => mgt_rx_header_locked_sync(i)
+    );
+    
+    sync_gbtbank_gbtrx_ready_inst : entity general_cores.gc_sync
+    port map (
+      clk_i     => frame_clk_i,
+      rst_n_a_i => '1',
+      d_i       => gbtbank_gbtrx_ready_s(i),
+      q_o       => gbtbank_gbtrx_ready_sync(i)
+    );
+    
+    sync_tx_aligned_inst : entity general_cores.gc_sync
+    port map (
+      clk_i     => frame_clk_i,
+      rst_n_a_i => '1',
+      d_i       => s_tx_aligned(i),
+      q_o       => s_tx_aligned_sync(i)
+    );
+    
+    sync_tx_aligned_val_inst : entity general_cores.gc_sync
+    port map (
+      clk_i     => frame_clk_i,
+      rst_n_a_i => '1',
+      d_i       => s_tx_aligned_val(i),
+      q_o       => s_tx_aligned_val_sync(i)
+    );
+    
+    sync_link_ready_inst : entity general_cores.gc_sync
+    port map (
+      clk_i     => frame_clk_i,
+      rst_n_a_i => '1',
+      d_i       => s_link_ready(i),
+      q_o       => s_link_ready_sync(i)
+    );
+
   end generate;