fix timeslice problem with multiple timeslices for rectangular design

git-svn-id: https://subversion.gsi.de/cbmsoft/cbmroot/trunk@15713 5a1b234a-d7ce-0410-9a93-fd649a8fa65c

trd/sim/CbmTrdDigitizer.cxx

@@ -200,7 +200,7 @@ void CbmTrdDigitizer::Exec(Option_t*)
   for(map<Int_t, CbmTrdModuleSim*>::iterator imod = fModuleMap.begin(); imod != fModuleMap.end(); imod++) {
     // in streaming mode flush buffers only up to a certain point in time wrt to current event time (allow for event pile-ups)
     //printf("Processing data for module %d\n", imod->first);
-    if(IsTimeBased()) nDigis += imod->second->FlushBuffer(fCurrentEventTime);  
+    if(IsTimeBased() && !fConverter->GetSetter()) nDigis += imod->second->FlushBuffer(fCurrentEventTime);  
     // in event-by-event mode flush all buffers     
     else imod->second->FlushBuffer();                               
     imod->second->GetCounters(n0, n1, n2);