1. 10 Nov, 2021 1 commit
  2. 09 Nov, 2021 5 commits
  3. 26 Oct, 2021 1 commit
  4. 23 Aug, 2021 1 commit
  5. 11 Aug, 2021 1 commit
  6. 09 Aug, 2021 2 commits
  7. 02 Jul, 2021 2 commits
  8. 08 Jun, 2021 1 commit
  9. 01 Jun, 2021 1 commit
  10. 20 Apr, 2021 1 commit
  11. 24 Mar, 2021 1 commit
    • Thomas Gessler's avatar
      XCKU MGTs: Set DISABLE_LOC_XDC to 1 · 1a8b3a12
      Thomas Gessler authored
      This (undocumented?) feature disables the insertion of MGT location
      constraints in the generated XDC files, so that identical transceiver
      cores can be instantiated multiple times without triggering critical
      warnings and causing problems later.
      1a8b3a12
  12. 17 Mar, 2021 2 commits
  13. 13 Jan, 2021 1 commit
  14. 19 Nov, 2020 5 commits
  15. 08 Oct, 2020 2 commits
  16. 30 Sep, 2020 2 commits
    • Thomas Gessler's avatar
      1f7e73b4
    • Thomas Gessler's avatar
      XCKU MGTs: Change from quads to individual links · 10eaa14a
      Thomas Gessler authored
      This makes it easier to run the transceivers within a single quad as
      individual links with separate line rates. Additional changes:
      
      - Change from QPLL to CPLLs.
      - Provide a single top entity for multiple possible
        frequency/reference-clock combinations.
      - Remove GT reset logic and rely on the TrbNet reset logic. This is not
        fully compatible with GTH cores. In particular, RX PCS reset must be
        ignored. Otherwise, RX allow is asserted too early, and faulty data
        reaches the RX control state machine.
      - Change the default equalizer mode to LPM, which is more reliable that
        DFE for 8b10b data with non-random sequences.
      - Change the clock-correction sequences to 4 words:
            (K)BC (D)C5 (K)BC (D)50
        and (K)BC (D)50 (K)BC (D)50
      10eaa14a
  17. 18 Sep, 2020 1 commit
  18. 11 Sep, 2020 2 commits
    • Thomas Gessler's avatar
      Overhaul clocking for XCKU MGTs · 216fd000
      Thomas Gessler authored
      The clock inputs and outputs are now exposed to the instantiating layer.
      This allows more flexible clocking schemes, including a completely
      synchrounous system with multiple quads.
      
      The reference-clock frequency is now set 100 MHz, so that it matches the
      user-clock frequency.
      
      The single-GT version is removed to simplify maintenance. Where needed,
      it can be replaced by the quad version.
      216fd000
    • Thomas Gessler's avatar
      cb9fbff9
  19. 04 Sep, 2020 1 commit
  20. 31 Aug, 2020 1 commit
  21. 24 Aug, 2020 1 commit
  22. 22 Aug, 2020 1 commit
  23. 17 Aug, 2020 1 commit
  24. 10 Aug, 2020 2 commits
  25. 07 Aug, 2020 1 commit