Commit cb10d049 authored by Michael Boehmer's avatar Michael Boehmer
Browse files

LPF updated, cleaned up constraints

parent d2a431c3
-w
-l 5
-s 10
-t 13 # seed setting here!
-t 9 # seed setting here! # 13 11
-c 2
-e 2
-i 10
......
......@@ -7,37 +7,48 @@ BLOCK RD_DURING_WR_PATHS ;
# Basic Settings
#################################################################
FREQUENCY PORT CLK_200 200 MHz;
FREQUENCY PORT CLK_125 125 MHz;
FREQUENCY PORT CLK_EXT 200 MHz;
FREQUENCY PORT "CLK_200" 200.000 MHz;
FREQUENCY PORT "CLK_125" 125.000 MHz;
FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
# FREQUENCY NET "med_stat_debug[11]" 200 MHz;
# read from SCI can be delayed due to long read strobe
MULTICYCLE FROM ASIC THE_MEDIA_INTERFACE/gen_SERDES.THE_SERDES/serdes_sync_0_125M_inst/DCU0_inst PIN D_SCIRDATA* 15 ns;
# write strobe can be delayed due to A/D being stable after access
MULTICYCLE TO ASIC THE_MEDIA_INTERFACE/gen_SERDES.THE_SERDES/serdes_sync_0_125M_inst/DCU0_inst PIN D_SCIWSTN 15 ns;
FREQUENCY NET "med2int_0.clk_full" 200 MHz;
# FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz;
# relax reset
MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns;
REGION "MEDIA" "R81C44D" 13 25;
LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ;
GSR_NET NET "GSR_N";
BLOCK PATH TO PORT "LED*";
BLOCK PATH TO PORT "PROGRAMN";
########################################
# OLD STUFF
########################################
#BLOCK PATH TO PORT "TEMP_LINE";
#BLOCK PATH FROM PORT "TEMP_LINE";
#BLOCK PATH TO PORT "TEST_LINE*";
#GSR_NET NET "clear_i";
#FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
#FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
#FREQUENCY NET "med2int_0.clk_full" 200 MHz;
BLOCK PATH TO PORT "LED*";
BLOCK PATH TO PORT "PROGRAMN";
BLOCK PATH TO PORT "TEMP_LINE";
BLOCK PATH FROM PORT "TEMP_LINE";
BLOCK PATH TO PORT "TEST_LINE*";
#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns;
#MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns;
#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;
#MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;
MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns;
MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns;
GSR_NET NET "clear_i";
#MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns;
#MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns;
# LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ;
REGION "MEDIA" "R81C44D" 13 25;
LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ;
......@@ -199,8 +199,8 @@ trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and no
-- komma operation
RX_DLM_OUT => rx_dlm_i, --open,
RX_DLM_WORD_OUT => rx_dlm_word_i, --open,
TX_DLM_IN => '0',
TX_DLM_WORD_IN => x"00",
TX_DLM_IN => rx_dlm_i, --'0',
TX_DLM_WORD_IN => rx_dlm_word_i, --x"00",
RX_RST_OUT => open,
RX_RST_WORD_OUT => open,
TX_RST_IN => '0',
......
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