Jan Michel (c43c9b87) at 30 Nov 14:39
added invert functionality for trigger output signals, mt
Jan Michel (fc455fda) at 20 Nov 12:39
added dirich5d1, mt
Jan Michel (305e7680) at 20 Nov 12:36
dirich5s1 fixes, mt
Jan Michel (13358e0a) at 04 Apr 16:57
added I2C for Serdes, new reset routine and more stable CDR setting...
Jan Michel (19df87c5) at 17 Oct 18:25
added correct PLL for 200MHz calibration oscillator, mt
Jan Michel (ec31cfc5) at 08 Sep 12:14
no ADC, mt
Jan Michel (7f646e4e) at 08 Sep 12:11
fixed config.vhd for dirich5s and adapted pathes for gsi, mt
Jan Michel (1f096f58) at 09 Jul 08:45
Jan Michel (2a24f86d) at 15 Jun 11:44
adjust DiRICH trigger generation possibility to FF, similar to DiRI...
Jan Michel (5333638f) at 15 Jun 07:59
redesign of DiRICH5s1 trigger logic with explicit FlipFlop
Jan Michel (fa6c0e1f) at 08 Jun 12:07
add an or of all inputs with configuration options as trigger outpu...
Jan Michel (062ec6af) at 30 May 06:47
add simple (stretchable) multiplicity trigger for input channels fo...
... and 1 more commit
Jan Michel (f71c672c) at 04 May 14:32
Pll and reset handler for 240MHz on ECP5
Jan Michel (a06894cb) at 18 Jan 08:34
dirich5s: add nodelist for giessen lab setup
Jan Michel (656e1f07) at 18 Jan 08:31
add config compile for diriches with ECP5_5G
Jan Michel (5ecfc252) at 18 Jan 08:25
prepare combiner for potential shift to retransmission branch and a...
Jan Michel (1f096f58) at 12 Nov 07:26