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restructured hub generation and reduced needed functions. Now 2 data hubs are generated. A even number of downlinks is currently required.

fix of a bug in reset of trbnet from trbnet bridge. The sync from AGWB is mostly getting high for a few ns after reset. A timeout of a few ns resolves this issue for now.

add sync for preload signal with additional variable to suppress multiple read signals due to signal delay

minor change in reset of links in cri hub. more similar to standard streaming port entities of trbnet

set Trbnet Bridge Port to stream port. Reorder data in xilinx fifo wrapper to match lattice definition and allow for correct data transmission

This includes the addition of XCKU FIFO cores and some changes to the
HDL codes. This likely breaks the current simulation testbench, which
will have to be fixed in a future commit.

This reverts commit fa6e45f4.

- Remove XML files, which are apparently not required
- Set build directory for each core
- Add build directories and other files to gitignore file
- Set XCI options that are otherwise set during build

fix of crashung readout in case of triggers not together with in the DLM (CALIBRATION; seen while no DLM transmitted.). Now in case of 0xD trigger, the last DLM message is written to CTS and the readout is finished.

small changes to fix data written to fifo in hub logic. Before, first word was written to rx fifo in hub logic twice.

DCA bridge to trbNet in a UDP/GBE like manner. Testbench added. Only write direction is tested in simulation.

This achieves a deterministic phase of the downlink TX data with respect
to the reference clock (and system/CBM clock).

Add TX phase aligner core from CERN HPTD project:

https://gitlab.cern.ch/HPTD/tx_phase_aligner

This achieves TX phase alignment to a reference clock by the method
described in:

E. Mendes, S. Baron, C. Soos, J. Troska and P. Novellini, "Achieving
Picosecond-Level Phase Stability in Timing Distribution Systems With
Xilinx Ultrascale Transceivers," in IEEE Transactions on Nuclear
Science, vol. 67, no. 3, pp. 473-481, March 2020, doi:
10.1109/TNS.2020.2968112.

git-subtree-dir: hub_test/src/tx_phase_aligner
git-subtree-split: e92a060f338e99de064f09df812c65363268221b

init commit of two entitys to handle the slowcontrol between agwb/wishbone of cri and trbnet. Entities are based on trbnet to pci bridge and only an untested shelf. To be implemented

fix for data_ready signal and resulting 50% data acceptance. additional signal init values and reset for state machine