From ea7614397a6d650dc56ec4411c46f138f5980cf4 Mon Sep 17 00:00:00 2001
From: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>
Date: Wed, 14 Mar 2018 17:31:03 +0100
Subject: [PATCH] hdl: minor fixes to wb crossbar and wb gpio to reduce
synthesis and sim warnings
---
modules/wishbone/wb_crossbar/xwb_crossbar.vhd | 11 +++++++----
modules/wishbone/wb_gpio_port/wb_gpio_port.vhd | 3 ++-
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/modules/wishbone/wb_crossbar/xwb_crossbar.vhd b/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
index 265e349..687c3b8 100644
--- a/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
+++ b/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
@@ -6,7 +6,7 @@
-- Author : Wesley W. Terpstra
-- Company : GSI
-- Created : 2011-06-08
--- Last update: 2011-09-22
+-- Last update: 2018-03-14
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
@@ -129,9 +129,12 @@ architecture rtl of xwb_crossbar is
signal master_ie : t_wishbone_master_in_array(g_num_slaves downto 0);
signal master_oe : t_wishbone_master_out_array(g_num_slaves downto 0);
signal virtual_ERR : std_logic;
-
- signal matrix_old : matrix; -- Registered connection matrix
- signal matrix_new : matrix; -- The new values of the matrix
+
+ -- Registered connection matrix
+ signal matrix_old : matrix := (others => (others => '0'));
+
+ -- The new values of the matrix
+ signal matrix_new : matrix := (others => (others => '0'));
-- Either matrix_old or matrix_new, depending on g_registered
signal granted : matrix;
diff --git a/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd b/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
index 5b67513..239271e 100644
--- a/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
+++ b/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
@@ -5,7 +5,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-18
--- Last update: 2017-10-11
+-- Last update: 2018-03-14
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
@@ -325,6 +325,7 @@ begin
gpio_in(g_num_pins-1 downto 0) <= gpio_in_i;
gpio_in(gpio_in'LEFT downto g_num_pins) <= (others => '0');
gpio_oen_o <= dir_reg(g_num_pins-1 downto 0);
+ gpio_b <= (others => 'Z');
end generate gen_without_tristates;
wb_out.ack <= ack_int;
--
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