diff --git a/modules/wishbone/wb_crossbar/xwb_crossbar.vhd b/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
index 265e3495b9ebbcdb11882865bd2b7bb755a3bd7f..687c3b8d5ca93288b6e055b81d9c4b53e8d1fedc 100644
--- a/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
+++ b/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
@@ -6,7 +6,7 @@
 -- Author     : Wesley W. Terpstra
 -- Company    : GSI
 -- Created    : 2011-06-08
--- Last update: 2011-09-22
+-- Last update: 2018-03-14
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -129,9 +129,12 @@ architecture rtl of xwb_crossbar is
   signal master_ie : t_wishbone_master_in_array(g_num_slaves downto 0);
   signal master_oe : t_wishbone_master_out_array(g_num_slaves downto 0);
   signal virtual_ERR : std_logic;
-  
-  signal matrix_old : matrix; -- Registered connection matrix
-  signal matrix_new : matrix; -- The new values of the matrix
+
+   -- Registered connection matrix
+  signal matrix_old : matrix := (others => (others => '0'));
+
+   -- The new values of the matrix
+  signal matrix_new : matrix := (others => (others => '0'));
 
   -- Either matrix_old or matrix_new, depending on g_registered
   signal granted : matrix;
diff --git a/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd b/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
index 5b675134d5f3f4868a1e5f9ae75061124a8fe459..239271e75c143b8cc48ee10d7e3c68291c54371c 100644
--- a/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
+++ b/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
@@ -5,7 +5,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN BE-Co-HT
 -- Created    : 2010-05-18
--- Last update: 2017-10-11
+-- Last update: 2018-03-14
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'87
 -------------------------------------------------------------------------------
@@ -325,6 +325,7 @@ begin
     gpio_in(g_num_pins-1 downto 0) <= gpio_in_i;
     gpio_in(gpio_in'LEFT downto g_num_pins) <= (others => '0');
     gpio_oen_o                     <= dir_reg(g_num_pins-1 downto 0);
+    gpio_b                         <= (others => 'Z');
   end generate gen_without_tristates;
 
   wb_out.ack   <= ack_int;