From e7c5ad9f3522b241b30c8a2a691f6823547a2013 Mon Sep 17 00:00:00 2001
From: Dimitris Lampridis <dimitris.lampridis@cern.ch>
Date: Fri, 8 Jun 2018 11:29:19 +0200
Subject: [PATCH] Further relicensing to Solderpad v2 for all files used by
masterFIP
---
modules/common/gc_ds182x_interface.vhd | 49 +++++++------
modules/common/gc_dyn_extend_pulse.vhd | 59 ++++++----------
modules/common/gc_glitch_filt.vhd | 70 ++++++-------------
modules/common/gc_pulse_synchronizer.vhd | 44 +++++-------
modules/common/gc_sync_ffs.vhd | 42 +++++------
modules/common/gc_sync_register.vhd | 46 +++++-------
modules/common/gencores_pkg.vhd | 67 ++++++------------
.../genrams/common/inferred_async_fifo.vhd | 45 ++++++------
modules/genrams/common/inferred_sync_fifo.vhd | 45 ++++++------
.../genrams/generic/generic_async_fifo.vhd | 46 ++++++------
modules/genrams/generic/generic_sync_fifo.vhd | 46 ++++++------
modules/genrams/genram_pkg.vhd | 54 ++++++--------
modules/genrams/memory_loader_pkg.vhd | 24 +++++++
modules/genrams/xilinx/generic_dpram.vhd | 48 +++++--------
.../xilinx/generic_dpram_dualclock.vhd | 47 +++++--------
.../xilinx/generic_dpram_sameclock.vhd | 47 +++++--------
.../genrams/xilinx/generic_dpram_split.vhd | 39 +++++------
modules/wishbone/wb_crossbar/sdb_rom.vhd | 26 +++++++
modules/wishbone/wb_crossbar/xwb_crossbar.vhd | 48 ++++++-------
.../wishbone/wb_crossbar/xwb_sdb_crossbar.vhd | 26 +++++++
modules/wishbone/wb_remapper/xwb_remapper.vhd | 55 ++++++---------
.../wb_slave_adapter/wb_slave_adapter.vhd | 41 +++++------
modules/wishbone/wb_vic/vic_prio_enc.vhd | 24 +++++++
modules/wishbone/wb_vic/wb_slave_vic.vhd | 35 +++++++---
modules/wishbone/wb_vic/wb_slave_vic.wb | 27 ++++++-
modules/wishbone/wb_vic/wb_vic.vhd | 56 ++++++---------
modules/wishbone/wb_vic/xwb_vic.vhd | 56 ++++++---------
modules/wishbone/wbgen2/wbgen2_pkg.vhd | 34 ++++-----
modules/wishbone/wishbone_pkg.vhd | 45 ++++++------
29 files changed, 628 insertions(+), 663 deletions(-)
diff --git a/modules/common/gc_ds182x_interface.vhd b/modules/common/gc_ds182x_interface.vhd
index 9168423..27f2fa5 100644
--- a/modules/common/gc_ds182x_interface.vhd
+++ b/modules/common/gc_ds182x_interface.vhd
@@ -1,28 +1,27 @@
----------------------------------------------------------------------------------------------------
--- |
--- one wire temperature & unique id interface for DS1822 and DS1820 |
--- |
----------------------------------------------------------------------------------------------------
--- File gc_ds182x_interface.vhd |
--- |
--- Description Interface with the serial ID + Thermometer DS1822, DS1820 |
--- Notes: Started from the DS2401 interface. |
--- |
--- Authors Pablo Antonio Alvarez Sanchez |
----------------------------------------------------------------------------------------------------
-
----------------------------------------------------------------------------------------------------
--- GNU LESSER GENERAL PUBLIC LICENSE |
--- ------------------------------------ |
--- This source file is free software; you can redistribute it and/or modify it under the terms of |
--- the GNU Lesser General Public License as published by the Free Software Foundation; either |
--- version 2.1 of the License, or (at your option) any later version. |
--- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
--- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
--- See the GNU Lesser General Public License for more details. |
--- You should have received a copy of the GNU Lesser General Public License along with this |
--- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
----------------------------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name: gc_ds182x_interface
+--
+-- description: one wire temperature & unique id interface for
+-- DS1822 and DS1820.
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2013-2018
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
diff --git a/modules/common/gc_dyn_extend_pulse.vhd b/modules/common/gc_dyn_extend_pulse.vhd
index b1ad687..a5761dd 100644
--- a/modules/common/gc_dyn_extend_pulse.vhd
+++ b/modules/common/gc_dyn_extend_pulse.vhd
@@ -1,44 +1,27 @@
--------------------------------------------------------------------------------
--- Title : Pulse width extender
--- Project : General Cores library
--------------------------------------------------------------------------------
--- File : gc_extend_pulse.vhd
--- Author : Tomasz Wlostowski
--- Company : CERN
--- Created : 2009-09-01
--- Last update: 2012-06-19
--- Platform : FPGA-generic
--- Standard : VHDL '93
--------------------------------------------------------------------------------
--- Description:
--- Synchronous pulse extender. Generates a pulse of programmable width upon
--- detection of a rising edge in the input.
--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
--
--- Copyright (c) 2009-2011 CERN
+-- unit name: gc_dyn_extend_pulse
--
--- This source file is free software; you can redistribute it
--- and/or modify it under the terms of the GNU Lesser General
--- Public License as published by the Free Software Foundation;
--- either version 2.1 of the License, or (at your option) any
--- later version.
+-- description: Synchronous pulse extender. Generates a pulse of programmable
+-- width upon detection of a rising edge in the input.
--
--- This source is distributed in the hope that it will be
--- useful, but WITHOUT ANY WARRANTY; without even the implied
--- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
--- PURPOSE. See the GNU Lesser General Public License for more
--- details.
---
--- You should have received a copy of the GNU Lesser General
--- Public License along with this source; if not, download it
--- from http://www.gnu.org/licenses/lgpl-2.1.html
---
--------------------------------------------------------------------------------
--- Revisions :
--- Date Version Author Description
--- 2009-09-01 0.9 twlostow Created
--- 2011-04-18 1.0 twlostow Added comments & header
--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Copyright CERN 209-2018
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
diff --git a/modules/common/gc_glitch_filt.vhd b/modules/common/gc_glitch_filt.vhd
index 1710dc6..97107c1 100644
--- a/modules/common/gc_glitch_filt.vhd
+++ b/modules/common/gc_glitch_filt.vhd
@@ -1,41 +1,29 @@
---==============================================================================
--- CERN (BE-CO-HT)
--- Glitch filter with selectable length
---==============================================================================
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
--
--- author: Theodor Stana (t.stana@cern.ch)
+-- unit name: gc_glitch_filt
--
--- date of creation: 2013-03-12
+-- description: Glitch filter with selectable length, consisting of a set of
+-- chained flip-flops followed by a comparator. The comparator toggles to '1'
+-- when all FFs in the chain are '1' and respectively to '0' when all the FFS
+-- in the chain are '0'.
--
--- version: 1.0
---
--- description:
--- Glitch filter consisting of a set of chained flip-flops followed by a
--- comparator. The comparator toggles to '1' when all FFs in the chain are
--- '1' and respectively to '0' when all the FFS in the chain are '0'.
---
--- dependencies:
---
--- references:
---
---==============================================================================
--- GNU LESSER GENERAL PUBLIC LICENSE
---==============================================================================
--- This source file is free software; you can redistribute it and/or modify it
--- under the terms of the GNU Lesser General Public License as published by the
--- Free Software Foundation; either version 2.1 of the License, or (at your
--- option) any later version. This source is distributed in the hope that it
--- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
--- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
--- See the GNU Lesser General Public License for more details. You should have
--- received a copy of the GNU Lesser General Public License along with this
--- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---==============================================================================
--- last changes:
--- 2013-03-12 Theodor Stana t.stana@cern.ch File created
---==============================================================================
--- TODO: -
---==============================================================================
+--------------------------------------------------------------------------------
+-- Copyright CERN 2013-2018
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
@@ -69,19 +57,10 @@ end entity gc_glitch_filt;
architecture behav of gc_glitch_filt is
- --============================================================================
- -- Signal declarations
- --============================================================================
signal glitch_filt : std_logic_vector(g_len downto 0);
---==============================================================================
--- architecture begin
---==============================================================================
begin
- --============================================================================
- -- Glitch filtration logic
- --============================================================================
glitch_filt(0) <= dat_i;
-- Generate glitch filter FFs when the filter length is > 0
@@ -113,6 +92,3 @@ begin
end process p_output;
end architecture behav;
---==============================================================================
--- architecture end
---==============================================================================
diff --git a/modules/common/gc_pulse_synchronizer.vhd b/modules/common/gc_pulse_synchronizer.vhd
index 5d11548..eaa9759 100644
--- a/modules/common/gc_pulse_synchronizer.vhd
+++ b/modules/common/gc_pulse_synchronizer.vhd
@@ -1,37 +1,27 @@
--------------------------------------------------------------------------------
--- Title : Pulse synchronizer
--- Project : General Cores Library
--------------------------------------------------------------------------------
--- File : gc_pulse_synchronizer.vhd
--- Author : Tomasz Wlostowski
--- Company : CERN BE-CO-HT
--- Created : 2012-01-10
--- Last update: 2012-08-29
--- Platform : FPGA-generic
--- Standard : VHDL'93
--------------------------------------------------------------------------------
--- Description: Full feedback pulse synchronizer (works independently of the
--- input/output clock domain frequency ratio)
--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name: gc_pulse_synchronizer
--
--- Copyright (c) 2012 CERN / BE-CO-HT
+-- description: Full feedback pulse synchronizer (works independently of the
+-- input/output clock domain frequency ratio)
--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2012-2018
+--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
--- License, Version 0.51 (the “Licenseâ€) (which enables you, at your option,
--- to treat this file as licensed under the Apache License 2.0); you may not
--- use this file except in compliance with the License. You may obtain a copy
--- of the License at http://solderpad.org/licenses/SHL-0.51.
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
--- “AS IS†BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
---
--------------------------------------------------------------------------------
--- Revisions :
--- Date Version Author Description
--- 2012-01-12 1.0 twlostow Created
--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
diff --git a/modules/common/gc_sync_ffs.vhd b/modules/common/gc_sync_ffs.vhd
index 045235c..a870091 100644
--- a/modules/common/gc_sync_ffs.vhd
+++ b/modules/common/gc_sync_ffs.vhd
@@ -1,36 +1,26 @@
--------------------------------------------------------------------------------
--- Title : Synchronizer chain
--- Project : White Rabbit
--------------------------------------------------------------------------------
--- File : gc_sync_ffs.vhd
--- Author : Tomasz Wlostowski
--- Company : CERN BE-Co-HT
--- Created : 2010-06-14
--- Last update: 2017-02-03
--- Platform : FPGA-generic
--- Standard : VHDL'87
--------------------------------------------------------------------------------
--- Description: Synchronizer chain and edge detector.
--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
--
--- Copyright (c) 2009 - 2017 CERN
+-- unit name: gc_sync_ffs
--
+-- description: Synchronizer chain and edge detector.
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2010-2018
+--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
--- License, Version 0.51 (the “Licenseâ€) (which enables you, at your option,
--- to treat this file as licensed under the Apache License 2.0); you may not
--- use this file except in compliance with the License. You may obtain a copy
--- of the License at http://solderpad.org/licenses/SHL-0.51.
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
--- “AS IS†BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
---
--------------------------------------------------------------------------------
--- Revisions :
--- Date Version Author Description
--- 2010-06-14 1.0 twlostow Created
--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
diff --git a/modules/common/gc_sync_register.vhd b/modules/common/gc_sync_register.vhd
index 8d43ef4..1f21662 100644
--- a/modules/common/gc_sync_register.vhd
+++ b/modules/common/gc_sync_register.vhd
@@ -1,35 +1,25 @@
--------------------------------------------------------------------------------
--- Title : Parametrized synchronizer
--- Project : General Cores
--------------------------------------------------------------------------------
--- File : gc_sync_register.vhd
--- Company : CERN
--- Platform : FPGA-generics
--- Standard : VHDL '93
--------------------------------------------------------------------------------
--- Copyright (c) 2014-2017 CERN
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
--
--- This source file is free software; you can redistribute it
--- and/or modify it under the terms of the GNU Lesser General
--- Public License as published by the Free Software Foundation;
--- either version 2.1 of the License, or (at your option) any
--- later version.
+-- unit name: gc_sync_register
--
--- This source is distributed in the hope that it will be
--- useful, but WITHOUT ANY WARRANTY; without even the implied
--- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
--- PURPOSE. See the GNU Lesser General Public License for more
--- details.
+-- description: Parametrized synchronizer.
--
--- You should have received a copy of the GNU Lesser General
--- Public License along with this source; if not, download it
--- from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--- Modifications:
--- 2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
--- * added ASYNC_REG attribute for better timing analysis/simulation
--- in Xilinx tools
+-- Copyright CERN 2014-2018
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
--------------------------------------------------------------------------------
library ieee;
diff --git a/modules/common/gencores_pkg.vhd b/modules/common/gencores_pkg.vhd
index 7d6e017..aef4977 100644
--- a/modules/common/gencores_pkg.vhd
+++ b/modules/common/gencores_pkg.vhd
@@ -1,52 +1,27 @@
--------------------------------------------------------------------------------
--- Title : General cores VHDL package
--- Project : General Cores library
--------------------------------------------------------------------------------
--- File : gencores_pkg.vhd
--- Author : Tomasz Wlostowski
--- Theodor-Adrian Stana
--- Matthieu Cattin
--- Evangelia Gousiou
--- Dimitrios Lampridis
--- Company : CERN
--- Created : 2009-09-01
--- Last update: 2018-03-23
--- Platform : FPGA-generic
--- Standard : VHDL '93
--------------------------------------------------------------------------------
--- Description:
--- Package incorporating simple VHDL modules and functions, which are used
--- in the WR and other OHWR projects.
--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
--
--- Copyright (c) 2009-2016 CERN
+-- unit name: gencores_pkg
--
--- This source file is free software; you can redistribute it
--- and/or modify it under the terms of the GNU Lesser General
--- Public License as published by the Free Software Foundation;
--- either version 2.1 of the License, or (at your option) any
--- later version.
+-- description: Package incorporating simple VHDL modules and functions,
+-- which are used in OHWR projects.
--
--- This source is distributed in the hope that it will be
--- useful, but WITHOUT ANY WARRANTY; without even the implied
--- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
--- PURPOSE. See the GNU Lesser General Public License for more
--- details.
---
--- You should have received a copy of the GNU Lesser General
--- Public License along with this source; if not, download it
--- from http://www.gnu.org/licenses/lgpl-2.1.html
---
--------------------------------------------------------------------------------
--- Revisions :
--- Date Version Author Description
--- 2009-09-01 0.9 twlostow Created
--- 2011-04-18 1.0 twlostow Added comments & header
--- 2013-11-20 1.1 tstana Added glitch filter and I2C slave
--- 2014-03-14 1.2 mcattin Added dynamic glitch filter
--- 2014-03-20 1.3 mcattin Added bicolor led controller
--- 2016-09-26 1.4 egousiou Added one-wire DS182x interface
--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Copyright CERN 2009-2018
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
diff --git a/modules/genrams/common/inferred_async_fifo.vhd b/modules/genrams/common/inferred_async_fifo.vhd
index bf24ea5..b65062a 100644
--- a/modules/genrams/common/inferred_async_fifo.vhd
+++ b/modules/genrams/common/inferred_async_fifo.vhd
@@ -1,26 +1,29 @@
--------------------------------------------------------------------------------
--- Title : Parametrizable asynchronous FIFO (Generic version)
--- Project : Generics RAMs and FIFOs collection
--------------------------------------------------------------------------------
--- File : generic_async_fifo.vhd
--- Author : Tomasz Wlostowski
--- Company : CERN BE-CO-HT
--- Created : 2011-01-25
--- Last update: 2014-07-31
--- Platform :
--- Standard : VHDL'93
--------------------------------------------------------------------------------
--- Description: Dual-clock asynchronous FIFO.
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name: inferred_async_fifo
+--
+-- description: Parametrizable asynchronous FIFO (Generic version).
+-- Dual-clock asynchronous FIFO.
-- - configurable data width and size
-- - configurable full/empty/almost full/almost empty/word count signals
--------------------------------------------------------------------------------
--- Copyright (c) 2011 CERN
--------------------------------------------------------------------------------
--- Revisions :
--- Date Version Author Description
--- 2011-01-25 1.0 twlostow Created
--------------------------------------------------------------------------------
-
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2011-2018
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
diff --git a/modules/genrams/common/inferred_sync_fifo.vhd b/modules/genrams/common/inferred_sync_fifo.vhd
index c70a830..ed7de11 100644
--- a/modules/genrams/common/inferred_sync_fifo.vhd
+++ b/modules/genrams/common/inferred_sync_fifo.vhd
@@ -1,26 +1,29 @@
--------------------------------------------------------------------------------
--- Title : Parametrizable synchronous FIFO (Generic version)
--- Project : Generics RAMs and FIFOs collection
--------------------------------------------------------------------------------
--- File : generic_sync_fifo_std.vhd
--- Author : Tomasz Wlostowski
--- Company : CERN BE-CO-HT
--- Created : 2011-01-25
--- Last update: 2017-02-03
--- Platform :
--- Standard : VHDL'93
--------------------------------------------------------------------------------
--- Description: Single-clock FIFO.
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name: inferred_sync_fifo
+--
+-- description: Parametrizable synchronous FIFO (Generic version).
+-- Single-clock FIFO.
-- - configurable data width and size
-- - configurable full/empty/almost full/almost empty/word count signals
--------------------------------------------------------------------------------
--- Copyright (c) 2011-2017 CERN
--------------------------------------------------------------------------------
--- Revisions :
--- Date Version Author Description
--- 2011-01-25 1.0 twlostow Created
--------------------------------------------------------------------------------
-
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2011-2018
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
diff --git a/modules/genrams/generic/generic_async_fifo.vhd b/modules/genrams/generic/generic_async_fifo.vhd
index 66fce2f..42505c4 100644
--- a/modules/genrams/generic/generic_async_fifo.vhd
+++ b/modules/genrams/generic/generic_async_fifo.vhd
@@ -1,26 +1,30 @@
--------------------------------------------------------------------------------
--- Title : Parametrizable asynchronous FIFO (Generic version)
--- Project : Generics RAMs and FIFOs collection
--------------------------------------------------------------------------------
--- File : generic_async_fifo.vhd
--- Author : Tomasz Wlostowski
--- Company : CERN BE-CO-HT
--- Created : 2011-01-25
--- Last update: 2012-07-03
--- Platform :
--- Standard : VHDL'93
--------------------------------------------------------------------------------
--- Description: Dual-clock asynchronous FIFO.
+
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name: generic_async_fifo
+--
+-- description: Parametrizable asynchronous FIFO (Generic version).
+-- Dual-clock asynchronous FIFO.
-- - configurable data width and size
-- - configurable full/empty/almost full/almost empty/word count signals
--------------------------------------------------------------------------------
--- Copyright (c) 2011 CERN
--------------------------------------------------------------------------------
--- Revisions :
--- Date Version Author Description
--- 2011-01-25 1.0 twlostow Created
--------------------------------------------------------------------------------
-
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2011-2018
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
diff --git a/modules/genrams/generic/generic_sync_fifo.vhd b/modules/genrams/generic/generic_sync_fifo.vhd
index fecd088..b48cc42 100644
--- a/modules/genrams/generic/generic_sync_fifo.vhd
+++ b/modules/genrams/generic/generic_sync_fifo.vhd
@@ -1,27 +1,29 @@
--------------------------------------------------------------------------------
--- Title : Parametrizable synchronous FIFO (Xilinx version)
--- Project : Generics RAMs and FIFOs collection
--------------------------------------------------------------------------------
--- File : generic_sync_fifo.vhd
--- Author : Tomasz Wlostowski
--- Company : CERN BE-CO-HT
--- Created : 2011-01-25
--- Last update: 2012-07-03
--- Platform :
--- Standard : VHDL'93
--------------------------------------------------------------------------------
--- Description: Single-clock FIFO.
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name: generic_sync_fifo
+--
+-- description: Parametrizable synchronous FIFO (Generic version).
+-- Single-clock FIFO.
-- - configurable data width and size
--- - "show ahead" mode
-- - configurable full/empty/almost full/almost empty/word count signals
--------------------------------------------------------------------------------
--- Copyright (c) 2011 CERN
--------------------------------------------------------------------------------
--- Revisions :
--- Date Version Author Description
--- 2011-01-25 1.0 twlostow Created
--------------------------------------------------------------------------------
-
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2011-2018
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
diff --git a/modules/genrams/genram_pkg.vhd b/modules/genrams/genram_pkg.vhd
index c212bbf..3c74975 100644
--- a/modules/genrams/genram_pkg.vhd
+++ b/modules/genrams/genram_pkg.vhd
@@ -1,40 +1,26 @@
--------------------------------------------------------------------------------
--- Title : Main package file
--- Project : Generics RAMs and FIFOs collection
--------------------------------------------------------------------------------
--- File : genram_pkg.vhd
--- Author : Tomasz Wlostowski
--- Company : CERN BE-CO-HT
--- Created : 2011-01-25
--- Last update: 2013-10-30
--- Platform :
--- Standard : VHDL'93
--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
--
--- Copyright (c) 2011 CERN
+-- unit name: genram_pkg
--
--- This source file is free software; you can redistribute it
--- and/or modify it under the terms of the GNU Lesser General
--- Public License as published by the Free Software Foundation;
--- either version 2.1 of the License, or (at your option) any
--- later version.
+-- description: Generics RAMs and FIFOs collection
--
--- This source is distributed in the hope that it will be
--- useful, but WITHOUT ANY WARRANTY; without even the implied
--- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
--- PURPOSE. See the GNU Lesser General Public License for more
--- details.
---
--- You should have received a copy of the GNU Lesser General
--- Public License along with this source; if not, download it
--- from http://www.gnu.org/licenses/lgpl-2.1.html
---
--------------------------------------------------------------------------------
--- Revisions :
--- Date Version Author Description
--- 2011-01-25 1.0 twlostow Created
--------------------------------------------------------------------------------
-
+--------------------------------------------------------------------------------
+-- Copyright CERN 2011-2018
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
diff --git a/modules/genrams/memory_loader_pkg.vhd b/modules/genrams/memory_loader_pkg.vhd
index 5bb1da6..07a8910 100644
--- a/modules/genrams/memory_loader_pkg.vhd
+++ b/modules/genrams/memory_loader_pkg.vhd
@@ -1,3 +1,27 @@
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name: memory_loader_pkg
+--
+-- description: RAM initialization package
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2011-2018
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
+
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
diff --git a/modules/genrams/xilinx/generic_dpram.vhd b/modules/genrams/xilinx/generic_dpram.vhd
index 2b166cf..b9e4531 100644
--- a/modules/genrams/xilinx/generic_dpram.vhd
+++ b/modules/genrams/xilinx/generic_dpram.vhd
@@ -1,43 +1,33 @@
--------------------------------------------------------------------------------
--- Title : Parametrizable dual-port synchronous RAM (Xilinx version)
--- Project : Generics RAMs and FIFOs collection
--------------------------------------------------------------------------------
--- File : generic_dpram.vhd
--- Author : Tomasz Wlostowski
--- Company : CERN BE-CO-HT
--- Created : 2011-01-25
--- Last update: 2012-03-16
--- Platform :
--- Standard : VHDL'93
--------------------------------------------------------------------------------
--- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name: generic_dpram
+--
+-- description: True dual-port synchronous RAM for Xilinx FPGAs with:
-- - configurable address and data bus width
-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
--- Todo:
+--
+-- todo:
-- - loading initial contents from file
-- - add support for read-first/write-first address conflict resulution (only
-- supported by Xilinx in VHDL templates)
--------------------------------------------------------------------------------
--- Copyright (c) 2011 CERN
--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2011-2018
+--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
--- License, Version 0.51 (the “Licenseâ€) (which enables you, at your option,
--- to treat this file as licensed under the Apache License 2.0); you may not
--- use this file except in compliance with the License. You may obtain a copy
--- of the License at http://solderpad.org/licenses/SHL-0.51.
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
--- “AS IS†BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
---
--------------------------------------------------------------------------------
--- Revisions :
--- Date Version Author Description
--- 2011-01-25 1.0 twlostow Created
--- 2012-03-13 1.1 wterpstra Added initial value as array
--------------------------------------------------------------------------------
-
+--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
diff --git a/modules/genrams/xilinx/generic_dpram_dualclock.vhd b/modules/genrams/xilinx/generic_dpram_dualclock.vhd
index 10e3b9b..c7e7d40 100644
--- a/modules/genrams/xilinx/generic_dpram_dualclock.vhd
+++ b/modules/genrams/xilinx/generic_dpram_dualclock.vhd
@@ -1,42 +1,33 @@
--------------------------------------------------------------------------------
--- Title : Parametrizable dual-port synchronous RAM (Xilinx version)
--- Project : Generics RAMs and FIFOs collection
--------------------------------------------------------------------------------
--- File : generic_dpram.vhd
--- Author : Tomasz Wlostowski
--- Company : CERN BE-CO-HT
--- Created : 2011-01-25
--- Last update: 2012-03-28
--- Platform :
--- Standard : VHDL'93
--------------------------------------------------------------------------------
--- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name: generic_dpram_dualclock
+--
+-- description: True dual-port synchronous RAM for Xilinx FPGAs with:
-- - configurable address and data bus width
-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
--- Todo:
+--
+-- todo:
-- - loading initial contents from file
-- - add support for read-first/write-first address conflict resulution (only
-- supported by Xilinx in VHDL templates)
--------------------------------------------------------------------------------
--- Copyright (c) 2011 CERN
--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2011-2018
+--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
--- License, Version 0.51 (the “Licenseâ€) (which enables you, at your option,
--- to treat this file as licensed under the Apache License 2.0); you may not
--- use this file except in compliance with the License. You may obtain a copy
--- of the License at http://solderpad.org/licenses/SHL-0.51.
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
--- “AS IS†BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
---
--------------------------------------------------------------------------------
--- Revisions :
--- Date Version Author Description
--- 2011-01-25 1.0 twlostow Created
--------------------------------------------------------------------------------
-
+--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
diff --git a/modules/genrams/xilinx/generic_dpram_sameclock.vhd b/modules/genrams/xilinx/generic_dpram_sameclock.vhd
index c1e2bfe..78e36b9 100644
--- a/modules/genrams/xilinx/generic_dpram_sameclock.vhd
+++ b/modules/genrams/xilinx/generic_dpram_sameclock.vhd
@@ -1,42 +1,33 @@
--------------------------------------------------------------------------------
--- Title : Parametrizable dual-port synchronous RAM (Xilinx version)
--- Project : Generics RAMs and FIFOs collection
--------------------------------------------------------------------------------
--- File : generic_dpram_sameclock.vhd
--- Author : Tomasz Wlostowski
--- Company : CERN BE-CO-HT
--- Created : 2011-01-25
--- Last update: 2015-03-30
--- Platform :
--- Standard : VHDL'93
--------------------------------------------------------------------------------
--- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name: generic_dpram_sameclock
+--
+-- description: True dual-port synchronous RAM for Xilinx FPGAs with:
-- - configurable address and data bus width
-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
--- Todo:
+--
+-- todo:
-- - loading initial contents from file
-- - add support for read-first/write-first address conflict resulution (only
-- supported by Xilinx in VHDL templates)
--------------------------------------------------------------------------------
--- Copyright (c) 2011 CERN
--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2011-2018
+--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
--- License, Version 0.51 (the “Licenseâ€) (which enables you, at your option,
--- to treat this file as licensed under the Apache License 2.0); you may not
--- use this file except in compliance with the License. You may obtain a copy
--- of the License at http://solderpad.org/licenses/SHL-0.51.
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
--- “AS IS†BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
---
--------------------------------------------------------------------------------
--- Revisions :
--- Date Version Author Description
--- 2011-01-25 1.0 twlostow Created
--------------------------------------------------------------------------------
-
+--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
diff --git a/modules/genrams/xilinx/generic_dpram_split.vhd b/modules/genrams/xilinx/generic_dpram_split.vhd
index a7722e4..3577963 100644
--- a/modules/genrams/xilinx/generic_dpram_split.vhd
+++ b/modules/genrams/xilinx/generic_dpram_split.vhd
@@ -1,15 +1,12 @@
--------------------------------------------------------------------------------
--- Title : Dual-port synchronous RAM with byte-write for Xilinx
--------------------------------------------------------------------------------
--- File : generic_dpram_split.vhd
--- Author : Grzegorz Daniluk
--- Company : CERN BE-CO-HT
--- Created : 2017-02-13
--- Last update: 2017-02-13
--- Platform :
--- Standard : VHDL'93
--------------------------------------------------------------------------------
--- Description:
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name: generic_dpram_split
+--
+-- description:
-- This module is 32-bit RAM with byte-write enables. It was created for Xilinx
-- FPGAs, since Xilinx ISE is unable to infer dual-port block-RAM with
-- byte-writes (e.g. based on generic_dpram_sameclock.vhd module). When
@@ -36,22 +33,20 @@
--
-- By "doesn't work" I mean that ISE does not fail during the synthesis, but RAM
-- does not get initialized.
--------------------------------------------------------------------------------
--- Copyright (c) 2017 CERN
--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2017-2018
+--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
--- License, Version 0.51 (the “Licenseâ€) (which enables you, at your option,
--- to treat this file as licensed under the Apache License 2.0); you may not
--- use this file except in compliance with the License. You may obtain a copy
--- of the License at http://solderpad.org/licenses/SHL-0.51.
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
--- “AS IS†BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
---
--------------------------------------------------------------------------------
-
+--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
diff --git a/modules/wishbone/wb_crossbar/sdb_rom.vhd b/modules/wishbone/wb_crossbar/sdb_rom.vhd
index 76c0de3..383381c 100644
--- a/modules/wishbone/wb_crossbar/sdb_rom.vhd
+++ b/modules/wishbone/wb_crossbar/sdb_rom.vhd
@@ -1,3 +1,29 @@
+--------------------------------------------------------------------------------
+-- GSI
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name: sdb_rom
+--
+-- author: Wesley W. Terpstra
+--
+-- description: SDB ROM for WB crossbar
+--
+--------------------------------------------------------------------------------
+-- Copyright GSI 2012-2018
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
+
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
diff --git a/modules/wishbone/wb_crossbar/xwb_crossbar.vhd b/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
index 9b2455f..8ba53a2 100644
--- a/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
+++ b/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
@@ -1,19 +1,14 @@
--------------------------------------------------------------------------------
--- Title : An MxS Wishbone crossbar switch
--- Project : General Cores Library (gencores)
--------------------------------------------------------------------------------
--- File : xwb_crossbar.vhd
--- Author : Wesley W. Terpstra
--- Company : GSI
--- Created : 2011-06-08
--- Last update: 2018-03-19
--- Platform : FPGA-generic
--- Standard : VHDL'93
--------------------------------------------------------------------------------
--- Description:
+--------------------------------------------------------------------------------
+-- GSI
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
--
--- An MxS Wishbone crossbar switch
---
+-- unit name: xwb_crossbar
+--
+-- author: Wesley W. Terpstra
+--
+-- description: An MxS Wishbone crossbar switch
-- All masters, slaves, and the crossbar itself must share the same WB clock.
-- All participants must support the same data bus width.
--
@@ -34,16 +29,19 @@
--
-- If g_registered = false, arbitration depth is added to M->S and S->M.
--
--------------------------------------------------------------------------------
--- Copyright (c) 2011 GSI / Wesley W. Terpstra
--------------------------------------------------------------------------------
--- Revisions :
--- Date Version Author Description
--- 2012-03-05 3.0 wterpstra made address generic and check overlap
--- 2011-11-04 2.0 wterpstra timing improvements
--- 2011-06-08 1.0 wterpstra import from SVN
--------------------------------------------------------------------------------
-
+--------------------------------------------------------------------------------
+-- Copyright GSI 2012-2018
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
diff --git a/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd b/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
index 010fe07..f35badc 100644
--- a/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
+++ b/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
@@ -1,3 +1,29 @@
+--------------------------------------------------------------------------------
+-- GSI
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name: xwb_sdb_crossbar
+--
+-- author: Wesley W. Terpstra
+--
+-- description: An MxS Wishbone crossbar switch (with SDB ROM)
+--
+--------------------------------------------------------------------------------
+-- Copyright GSI 2012-2018
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
+
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
diff --git a/modules/wishbone/wb_remapper/xwb_remapper.vhd b/modules/wishbone/wb_remapper/xwb_remapper.vhd
index 06273d7..75b2f77 100644
--- a/modules/wishbone/wb_remapper/xwb_remapper.vhd
+++ b/modules/wishbone/wb_remapper/xwb_remapper.vhd
@@ -1,40 +1,27 @@
--------------------------------------------------------------------------------
--- Title : Wishbone remapper
--- Project : General cores
--------------------------------------------------------------------------------
--- File : xwb_remapper.vhd
--- Author : Tomasz WÅ‚ostowski
--- Company : CERN BE-CO-HT
--- Created : 2014-04-01
--- Last update: 2018-03-23
--- Platform : FPGA-generic
--- Standard : VHDL'93
--------------------------------------------------------------------------------
--- Description:
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
--
--- Simple Wishbone bus address remapper. Remaps a certain range of addresses,
--- defined by base address and mask to another base address.
--------------------------------------------------------------------------------
+-- unit name: xwb_remapper
--
--- Copyright (c) 2014 CERN
+-- description: Simple Wishbone bus address remapper. Remaps a certain range
+-- of addresses defined by base address and mask to another base address.
--
--- This source file is free software; you can redistribute it
--- and/or modify it under the terms of the GNU Lesser General
--- Public License as published by the Free Software Foundation;
--- either version 2.1 of the License, or (at your option) any
--- later version.
---
--- This source is distributed in the hope that it will be
--- useful, but WITHOUT ANY WARRANTY; without even the implied
--- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
--- PURPOSE. See the GNU Lesser General Public License for more
--- details.
---
--- You should have received a copy of the GNU Lesser General
--- Public License along with this source; if not, download it
--- from http://www.gnu.org/licenses/lgpl-2.1.html
---
--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Copyright CERN 2014-2018
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
diff --git a/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd b/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
index 0251756..47ffd5e 100644
--- a/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
+++ b/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
@@ -1,32 +1,29 @@
--------------------------------------------------------------------------------
--- Title : Wishbone Slave Adapter
--- Project : General Cores
--------------------------------------------------------------------------------
--- File : wb_slave_adapter.vhd
--- Author : Tomasz Wlostowski
--- Company : CERN
--- Platform : FPGA-generics
--- Standard : VHDL '93
--------------------------------------------------------------------------------
--- Description:
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
--
--- universal "adapter"
--- pipelined <> classic
--- word-aligned/byte-aligned address
--------------------------------------------------------------------------------
--- Copyright (c) 2011-2017 CERN
+-- unit name: wb_slave_adapter
--
+-- description:
+-- universal "adapter"
+-- pipelined <> classic
+-- word-aligned/byte-aligned address
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2011-2018
+--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
--- License, Version 0.51 (the “Licenseâ€) (which enables you, at your option,
--- to treat this file as licensed under the Apache License 2.0); you may not
--- use this file except in compliance with the License. You may obtain a copy
--- of the License at http://solderpad.org/licenses/SHL-0.51.
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
--- “AS IS†BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
diff --git a/modules/wishbone/wb_vic/vic_prio_enc.vhd b/modules/wishbone/wb_vic/vic_prio_enc.vhd
index 4e2c132..ae1d9b2 100644
--- a/modules/wishbone/wb_vic/vic_prio_enc.vhd
+++ b/modules/wishbone/wb_vic/vic_prio_enc.vhd
@@ -1,3 +1,27 @@
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name: vic_prio_enc
+--
+-- description: Priority encoder for VIC
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2010-2018
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
+
library ieee;
use ieee.std_logic_1164.all;
diff --git a/modules/wishbone/wb_vic/wb_slave_vic.vhd b/modules/wishbone/wb_vic/wb_slave_vic.vhd
index b87df08..1f90c48 100644
--- a/modules/wishbone/wb_vic/wb_slave_vic.vhd
+++ b/modules/wishbone/wb_vic/wb_slave_vic.vhd
@@ -1,15 +1,32 @@
----------------------------------------------------------------------------------------
--- Title : Wishbone slave core for Vectored Interrupt Controller (VIC)
----------------------------------------------------------------------------------------
--- File : wb_slave_vic.vhd
--- Author : auto-generated by wbgen2 from wb_slave_vic.wb
--- Created : Thu Feb 14 10:35:14 2013
--- Standard : VHDL'87
----------------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name: wb_slave_vic
+--
+-- description: Wishbone slave core for Vectored Interrupt Controller (VIC)
+--
+-- Originally auto-generated by wbgen2 from wb_slave_vic.wb
+--
-- Warning!
-- This file has been hand-modified (for vector table pre-initialization).
-- Regenerating it using wbgen2 will break the design.
----------------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2013-2018
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
diff --git a/modules/wishbone/wb_vic/wb_slave_vic.wb b/modules/wishbone/wb_vic/wb_slave_vic.wb
index c9563f8..a2d6720 100644
--- a/modules/wishbone/wb_vic/wb_slave_vic.wb
+++ b/modules/wishbone/wb_vic/wb_slave_vic.wb
@@ -1,3 +1,28 @@
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name: wb_slave_vic
+--
+-- description: Wishbone slave core for Vectored Interrupt Controller (VIC)
+-- block layout (wbgen2)
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2013-2018
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
+
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
@@ -148,4 +173,4 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
-};
\ No newline at end of file
+};
diff --git a/modules/wishbone/wb_vic/wb_vic.vhd b/modules/wishbone/wb_vic/wb_vic.vhd
index 65fcf24..07d3401 100644
--- a/modules/wishbone/wb_vic/wb_vic.vhd
+++ b/modules/wishbone/wb_vic/wb_vic.vhd
@@ -1,15 +1,12 @@
-------------------------------------------------------------------------------
--- Title : Wishbone Vectored Interrupt Controller
--- Project : White Rabbit Switch
-------------------------------------------------------------------------------
--- Author : Tomasz Wlostowski
--- Company : CERN BE-Co-HT
--- Created : 2010-05-18
--- Last update: 2018-03-08
--- Platform : FPGA-generic
--- Standard : VHDL'87
--------------------------------------------------------------------------------
--- Description: Simple interrupt controller/multiplexer:
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name: wb_vic
+--
+-- description: Simple interrupt controller/multiplexer:
-- - designed to cooperate with wbgen2 peripherals Embedded Interrupt
-- Controllers (EICs)
-- - accepts 2 to 32 inputs (configurable using g_num_interrupts)
@@ -20,29 +17,20 @@
-- a configuration bit.
-- - interrupt is acknowledged by writing to EIC_EOIR register.
-- - register layout: see wb_vic.wb for details.
--------------------------------------------------------------------------------
--- Copyright (c) 2010 CERN
---
--- This source file is free software; you can redistribute it
--- and/or modify it under the terms of the GNU Lesser General
--- Public License as published by the Free Software Foundation;
--- either version 2.1 of the License, or (at your option) any
--- later version.
---
--- This source is distributed in the hope that it will be
--- useful, but WITHOUT ANY WARRANTY; without even the implied
--- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
--- PURPOSE. See the GNU Lesser General Public License for more
--- details.
--
--- You should have received a copy of the GNU Lesser General
--- Public License along with this source; if not, download it
--- from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
--- Revisions :
--- Date Version Author Description
--- 2010-05-18 1.0 twlostow Created
--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Copyright CERN 2010-2018
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
diff --git a/modules/wishbone/wb_vic/xwb_vic.vhd b/modules/wishbone/wb_vic/xwb_vic.vhd
index 62e4889..c107f9d 100644
--- a/modules/wishbone/wb_vic/xwb_vic.vhd
+++ b/modules/wishbone/wb_vic/xwb_vic.vhd
@@ -1,15 +1,12 @@
-------------------------------------------------------------------------------
--- Title : Wishbone Vectored Interrupt Controller
--- Project : White Rabbit Switch
-------------------------------------------------------------------------------
--- Author : Tomasz Wlostowski
--- Company : CERN BE-Co-HT
--- Created : 2010-05-18
--- Last update: 2018-03-08
--- Platform : FPGA-generic
--- Standard : VHDL'87
--------------------------------------------------------------------------------
--- Description: Simple interrupt controller/multiplexer:
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
+--
+-- unit name: xwb_vic
+--
+-- description: Simple interrupt controller/multiplexer:
-- - designed to cooperate with wbgen2 peripherals Embedded Interrupt
-- Controllers (EICs)
-- - accepts 2 to 32 inputs (configurable using g_num_interrupts)
@@ -20,29 +17,20 @@
-- a configuration bit.
-- - interrupt is acknowledged by writing to EIC_EOIR register.
-- - register layout: see wb_vic.wb for details.
--------------------------------------------------------------------------------
--- Copyright (c) 2010 CERN
---
--- This source file is free software; you can redistribute it
--- and/or modify it under the terms of the GNU Lesser General
--- Public License as published by the Free Software Foundation;
--- either version 2.1 of the License, or (at your option) any
--- later version.
---
--- This source is distributed in the hope that it will be
--- useful, but WITHOUT ANY WARRANTY; without even the implied
--- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
--- PURPOSE. See the GNU Lesser General Public License for more
--- details.
--
--- You should have received a copy of the GNU Lesser General
--- Public License along with this source; if not, download it
--- from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
--- Revisions :
--- Date Version Author Description
--- 2010-05-18 1.0 twlostow Created
--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Copyright CERN 2010-2018
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
diff --git a/modules/wishbone/wbgen2/wbgen2_pkg.vhd b/modules/wishbone/wbgen2/wbgen2_pkg.vhd
index c2d78ca..61737d2 100644
--- a/modules/wishbone/wbgen2/wbgen2_pkg.vhd
+++ b/modules/wishbone/wbgen2/wbgen2_pkg.vhd
@@ -1,26 +1,26 @@
--------------------------------------------------------------------------------
--- Title : WBGEN components
--- Project : General Cores
--------------------------------------------------------------------------------
--- File : wbgen2_pkg.vhd
--- Author : Tomasz Wlostowski
--- Company : CERN
--- Platform : FPGA-generics
--- Standard : VHDL '93
--------------------------------------------------------------------------------
--- Copyright (c) 2011-2012 CERN
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
--
+-- unit name: wbgen2_pkg
+--
+-- description: Component declaration for modules used by wbgen2
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2011-2018
+--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
--- License, Version 0.51 (the “Licenseâ€) (which enables you, at your option,
--- to treat this file as licensed under the Apache License 2.0); you may not
--- use this file except in compliance with the License. You may obtain a copy
--- of the License at http://solderpad.org/licenses/SHL-0.51.
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
--- “AS IS†BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
diff --git a/modules/wishbone/wishbone_pkg.vhd b/modules/wishbone/wishbone_pkg.vhd
index 7b26cd8..632c4d9 100644
--- a/modules/wishbone/wishbone_pkg.vhd
+++ b/modules/wishbone/wishbone_pkg.vhd
@@ -1,30 +1,27 @@
--------------------------------------------------------------------------------
--- Title : Wishbone package
--- Project : General Cores
--------------------------------------------------------------------------------
--- File : wishbone_pkg.vhd
--- Company : CERN
--- Platform : FPGA-generics
--- Standard : VHDL '93
--------------------------------------------------------------------------------
--- Copyright (c) 2011-2018 CERN
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- General Cores Library
+-- https://www.ohwr.org/projects/general-cores
+--------------------------------------------------------------------------------
--
--- This source file is free software; you can redistribute it
--- and/or modify it under the terms of the GNU Lesser General
--- Public License as published by the Free Software Foundation;
--- either version 2.1 of the License, or (at your option) any
--- later version.
+-- unit name: wishbone_pkg
--
--- This source is distributed in the hope that it will be
--- useful, but WITHOUT ANY WARRANTY; without even the implied
--- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
--- PURPOSE. See the GNU Lesser General Public License for more
--- details.
+-- description: Collection of Wishbone modules and definitions used in various
+-- OHWR projects.
--
--- You should have received a copy of the GNU Lesser General
--- Public License along with this source; if not, download it
--- from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- Copyright CERN 2011-2018
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
library ieee;
--
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