From e5e006a435da38ab636fe63dd9475ee9847e1c46 Mon Sep 17 00:00:00 2001
From: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>
Date: Tue, 20 Mar 2018 09:07:46 +0100
Subject: [PATCH] hdl: add option to wb gpio to bypass input synchronizers
---
.../wishbone/wb_gpio_port/wb_gpio_port.vhd | 31 ++++++++++++-------
.../wishbone/wb_gpio_port/xwb_gpio_port.vhd | 5 ++-
modules/wishbone/wishbone_pkg.vhd | 4 ++-
3 files changed, 26 insertions(+), 14 deletions(-)
diff --git a/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd b/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
index d27a79f..5147508 100644
--- a/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
+++ b/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
@@ -51,6 +51,7 @@ entity wb_gpio_port is
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_pins : natural range 1 to 256 := 32;
+ g_with_builtin_sync : boolean := true;
g_with_builtin_tristates : boolean := false
);
port(
@@ -134,18 +135,24 @@ begin
sel <= '1' when (unsigned(not wb_in.sel) = 0) else '0';
- GEN_SYNC_FFS : for i in 0 to g_num_pins-1 generate
- INPUT_SYNC : gc_sync_ffs
- generic map (
- g_sync_edge => "positive")
- port map (
- rst_n_i => rst_n_i,
- clk_i => clk_sys_i,
- data_i => gpio_in(i),
- synced_o => gpio_in_synced(i),
- npulse_o => open
- );
- end generate GEN_SYNC_FFS;
+ gen_with_sync: if g_with_builtin_sync generate
+ GEN_SYNC_FFS : for i in 0 to g_num_pins-1 generate
+ INPUT_SYNC : gc_sync_ffs
+ generic map (
+ g_sync_edge => "positive")
+ port map (
+ rst_n_i => rst_n_i,
+ clk_i => clk_sys_i,
+ data_i => gpio_in(i),
+ synced_o => gpio_in_synced(i),
+ npulse_o => open
+ );
+ end generate GEN_SYNC_FFS;
+ end generate gen_with_sync;
+
+ gen_without_sync: if not g_with_builtin_sync generate
+ gpio_in_synced <= gpio_in;
+ end generate gen_without_sync;
p_gen_write_mask : process(wb_in.adr)
begin
diff --git a/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd b/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
index b6d54e3..658f56e 100644
--- a/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
+++ b/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
@@ -5,7 +5,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-18
--- Last update: 2018-03-08
+-- Last update: 2018-03-19
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
@@ -38,6 +38,7 @@ entity xwb_gpio_port is
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_pins : natural range 1 to 256 := 32;
+ g_with_builtin_sync : boolean := true;
g_with_builtin_tristates : boolean := false
);
@@ -67,6 +68,7 @@ architecture rtl of xwb_gpio_port is
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_num_pins : natural range 1 to 256;
+ g_with_builtin_sync : boolean;
g_with_builtin_tristates : boolean);
port (
clk_sys_i : in std_logic;
@@ -93,6 +95,7 @@ begin -- rtl
g_num_pins => g_num_pins,
g_with_builtin_tristates => g_with_builtin_tristates,
g_interface_mode => g_interface_mode,
+ g_with_builtin_sync => g_with_builtin_sync,
g_address_granularity => g_address_granularity)
port map (
clk_sys_i => clk_sys_i,
diff --git a/modules/wishbone/wishbone_pkg.vhd b/modules/wishbone/wishbone_pkg.vhd
index 1d2d734..2f38efb 100644
--- a/modules/wishbone/wishbone_pkg.vhd
+++ b/modules/wishbone/wishbone_pkg.vhd
@@ -601,6 +601,7 @@ package wishbone_pkg is
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_pins : natural range 1 to 256;
+ g_with_builtin_sync : boolean := true;
g_with_builtin_tristates : boolean := false);
port (
clk_sys_i : in std_logic;
@@ -625,7 +626,8 @@ package wishbone_pkg is
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_pins : natural range 1 to 256;
- g_with_builtin_tristates : boolean);
+ g_with_builtin_sync : boolean := true;
+ g_with_builtin_tristates : boolean := false);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
--
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