diff --git a/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd b/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
index d27a79f08ab430734e0982f7d6b59c38477588c0..5147508e4417a269606ec0ff9ccb9cf1ae7061aa 100644
--- a/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
+++ b/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
@@ -51,6 +51,7 @@ entity wb_gpio_port is
     g_interface_mode         : t_wishbone_interface_mode      := CLASSIC;
     g_address_granularity    : t_wishbone_address_granularity := WORD;
     g_num_pins               : natural range 1 to 256         := 32;
+    g_with_builtin_sync      : boolean                        := true;
     g_with_builtin_tristates : boolean                        := false
     );
   port(
@@ -134,18 +135,24 @@ begin
 
   sel <= '1' when (unsigned(not wb_in.sel) = 0) else '0';
 
-  GEN_SYNC_FFS : for i in 0 to g_num_pins-1 generate
-    INPUT_SYNC : gc_sync_ffs
-      generic map (
-        g_sync_edge => "positive")
-      port map (
-        rst_n_i  => rst_n_i,
-        clk_i    => clk_sys_i,
-        data_i   => gpio_in(i),
-        synced_o => gpio_in_synced(i),
-        npulse_o => open
-        );
-  end generate GEN_SYNC_FFS;
+  gen_with_sync: if g_with_builtin_sync generate
+    GEN_SYNC_FFS : for i in 0 to g_num_pins-1 generate
+      INPUT_SYNC : gc_sync_ffs
+        generic map (
+          g_sync_edge => "positive")
+        port map (
+          rst_n_i  => rst_n_i,
+          clk_i    => clk_sys_i,
+          data_i   => gpio_in(i),
+          synced_o => gpio_in_synced(i),
+          npulse_o => open
+          );
+    end generate GEN_SYNC_FFS;
+  end generate gen_with_sync;
+
+  gen_without_sync: if not g_with_builtin_sync generate
+    gpio_in_synced <= gpio_in;
+  end generate gen_without_sync;
 
   p_gen_write_mask : process(wb_in.adr)
   begin
diff --git a/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd b/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
index b6d54e32cf55fe2bafd7ed9e6e53b5ef5f38a842..658f56ea7962a5b98b67352901e759ac1abd583e 100644
--- a/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
+++ b/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
@@ -5,7 +5,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN BE-Co-HT
 -- Created    : 2010-05-18
--- Last update: 2018-03-08
+-- Last update: 2018-03-19
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'87
 -------------------------------------------------------------------------------
@@ -38,6 +38,7 @@ entity xwb_gpio_port is
     g_interface_mode         : t_wishbone_interface_mode      := CLASSIC;
     g_address_granularity    : t_wishbone_address_granularity := WORD;
     g_num_pins               : natural range 1 to 256         := 32;
+    g_with_builtin_sync      : boolean                        := true;
     g_with_builtin_tristates : boolean                        := false
     );
 
@@ -67,6 +68,7 @@ architecture rtl of xwb_gpio_port is
       g_interface_mode         : t_wishbone_interface_mode;
       g_address_granularity    : t_wishbone_address_granularity;
       g_num_pins               : natural range 1 to 256;
+      g_with_builtin_sync      : boolean;
       g_with_builtin_tristates : boolean);
     port (
       clk_sys_i  : in    std_logic;
@@ -93,6 +95,7 @@ begin  -- rtl
       g_num_pins               => g_num_pins,
       g_with_builtin_tristates => g_with_builtin_tristates,
       g_interface_mode         => g_interface_mode,
+      g_with_builtin_sync      => g_with_builtin_sync,
       g_address_granularity    => g_address_granularity)
     port map (
       clk_sys_i  => clk_sys_i,
diff --git a/modules/wishbone/wishbone_pkg.vhd b/modules/wishbone/wishbone_pkg.vhd
index 1d2d734e34e9956af76cc28f7b85af36c20fe268..2f38efbf62a12c1dc538278da73c10d2e1c28d42 100644
--- a/modules/wishbone/wishbone_pkg.vhd
+++ b/modules/wishbone/wishbone_pkg.vhd
@@ -601,6 +601,7 @@ package wishbone_pkg is
       g_interface_mode         : t_wishbone_interface_mode      := CLASSIC;
       g_address_granularity    : t_wishbone_address_granularity := WORD;
       g_num_pins               : natural range 1 to 256;
+      g_with_builtin_sync      : boolean                        := true;
       g_with_builtin_tristates : boolean                        := false);
     port (
       clk_sys_i  : in    std_logic;
@@ -625,7 +626,8 @@ package wishbone_pkg is
       g_interface_mode         : t_wishbone_interface_mode      := CLASSIC;
       g_address_granularity    : t_wishbone_address_granularity := WORD;
       g_num_pins               : natural range 1 to 256;
-      g_with_builtin_tristates : boolean);
+      g_with_builtin_sync      : boolean                        := true;
+      g_with_builtin_tristates : boolean                        := false);
     port (
       clk_sys_i  : in    std_logic;
       rst_n_i    : in    std_logic;