diff --git a/doc/Makefile b/doc/Makefile index 7afa3f3213c04b792afb2727f9bc94970e9a4a57..2f5f04e20ac65a35768eb39aba226452721e7fb7 100644 --- a/doc/Makefile +++ b/doc/Makefile @@ -43,6 +43,9 @@ MAKEINFO ?= makeinfo all: images $(ALL) $(MAKE) terse + $(MAKE) -C gc_i2c_slave + $(MAKE) -C wb_i2c_bridge + $(MAKE) -C wb_xil_multiboot images:: if [ -d images ]; then $(MAKE) -C images || exit 1; fi diff --git a/doc/gc_i2c_slave/Makefile b/doc/gc_i2c_slave/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..f54084d450208980deadf3cd0b43f5baa06290ad --- /dev/null +++ b/doc/gc_i2c_slave/Makefile @@ -0,0 +1,14 @@ +FILE=gc_i2c_slave + +all: + $(MAKE) -C fig + pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex + bibtex $(FILE).aux + pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex + pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex + evince $(FILE).pdf & + +clean: + $(MAKE) -C fig clean + rm -rf *.aux *.dvi *.log $(FILE).pdf *.lof *.lot *.out *.toc *.bbl *.blg *.gz + diff --git a/doc/gc_i2c_slave/README.txt b/doc/gc_i2c_slave/README.txt new file mode 100644 index 0000000000000000000000000000000000000000..e69d1177f1e40e729e63801d1f69fcf7653bf564 --- /dev/null +++ b/doc/gc_i2c_slave/README.txt @@ -0,0 +1,4 @@ +Type 'make' to create your .pdf documentation file. + +You need Inkscape to make the documentation files: +sudo apt-get install inkscape \ No newline at end of file diff --git a/doc/gc_i2c_slave/cern-title.tex b/doc/gc_i2c_slave/cern-title.tex new file mode 100644 index 0000000000000000000000000000000000000000..8f5dbe8b4d93648f99b9297428c5da35a6410240 --- /dev/null +++ b/doc/gc_i2c_slave/cern-title.tex @@ -0,0 +1,25 @@ +\begin{titlepage} + +\vspace*{3cm} + +\noindent{\LARGE \textbf{I$^2$C Slave Core}} + +\noindent \rule{\textwidth}{.1cm} + +\hfill\today + +\vspace*{3cm} + +\begin{figure}[h] + \includegraphics[height=3cm]{fig/cern-logo} + \hfill + \includegraphics[height=3cm]{fig/ohwr-logo} +\end{figure} + +\vfill + +\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}} + +\noindent \rule{\textwidth}{.05cm} + +\end{titlepage} diff --git a/doc/gc_i2c_slave/fig/Makefile b/doc/gc_i2c_slave/fig/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..00fe82ab1dec0a92d0f8fbd96f7690b50f105166 --- /dev/null +++ b/doc/gc_i2c_slave/fig/Makefile @@ -0,0 +1,11 @@ +SRC = $(wildcard *.svg) +OBJS = $(SRC:.svg=.pdf) + +all: $(OBJS) + echo $(OBJS) + +%.pdf : %.svg + inkscape -f $< -A $@ + +clean : + rm -f *.pdf diff --git a/doc/gc_i2c_slave/fig/cern-logo.svg b/doc/gc_i2c_slave/fig/cern-logo.svg new file mode 100644 index 0000000000000000000000000000000000000000..470c7b0a157435f6443c68c4dd45248e68624585 --- /dev/null +++ b/doc/gc_i2c_slave/fig/cern-logo.svg @@ -0,0 +1,53 @@ +<?xml version="1.0" encoding="utf-8"?> +<!-- Generator: Adobe Illustrator 15.0.2, SVG Export Plug-In . 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a/doc/gc_i2c_slave/gc_i2c_slave.tex b/doc/gc_i2c_slave/gc_i2c_slave.tex new file mode 100644 index 0000000000000000000000000000000000000000..dc57a87e6fcd70a0c17ea25f9dfbf58aa847cc17 --- /dev/null +++ b/doc/gc_i2c_slave/gc_i2c_slave.tex @@ -0,0 +1,484 @@ +%============================================================================== +% Document header +%============================================================================== +\documentclass[a4paper,11pt]{article} + +% Color package +\usepackage[usenames,dvipsnames]{color} + +% Hyperrefs +\usepackage[ + colorlinks = true, + linkcolor = Mahogany, + citecolor = Mahogany, + urlcolor = blue, +]{hyperref} + +\usepackage{graphicx} +\usepackage{rotating} +\usepackage{multirow} + +\usepackage{longtable} + +% Header and footer customization +\usepackage{fancyhdr} +\pagestyle{fancy} +\fancyhead[L]{\nouppercase{\leftmark}} +\fancyhead[R]{} +\renewcommand{\footrulewidth}{0.4pt} + +%============================================================================== +% Start of document +%============================================================================== +\begin{document} + +%------------------------------------------------------------------------------ +% Title +%------------------------------------------------------------------------------ +\include{cern-title} + +%------------------------------------------------------------------------------ +% Revision history +%------------------------------------------------------------------------------ +\thispagestyle{empty} +\section*{Revision history} + +\centerline +{ + \begin{tabular}{l c p{.6\textwidth}} + \hline + \multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\ + \hline + 26-06-2013 & 0.01 & First draft \\ + 28-10-2013 & 0.02 & Changed PDF link colors \\ + \hline + \end{tabular} +} + +%------------------------------------------------------------------------------ +% Generate TOC and pagebreak after it +%------------------------------------------------------------------------------ +\pagebreak +\pagenumbering{roman} +\setcounter{page}{1} +\tableofcontents + +%------------------------------------------------------------------------------ +% List of figs, tables, abbrevs +%------------------------------------------------------------------------------ +\pagebreak +\listoffigures +\listoftables + +\section*{List of Abbreviations} +\begin{tabular}{l l} + ASIC & Application-Specific Integrated Circuit \\ + FPGA & Field-Programmable Gate Array \\ + I$^2$C & Inter-Integrated Circuit \\ + SCL & Serial CLock \\ + SDA & Serial DAta \\ +\end{tabular} + +%============================================================================== +% SEC: Intro +%============================================================================== +\pagebreak +\pagenumbering{arabic} +\setcounter{page}{1} +\section{Introduction} +\label{sec:intro} + +The \textit{i2c\_slave} VHDL module implements a simple I$^2$C +slave core capable of responding to I$^2$C transfers generated by a master. The module +is conceived to be controlled by an external module. Basic shifting of bits into the +module is handled during read transfers (from the slave's point of view), at the end of +which the user is presented with the received byte. Similarly, in the case of a write +transfer, the user inputs a byte to be sent, and the module handles shifting out of each +of the bits. The status of the module can be obtained via dedicated ports. + +The main features of the \textit{i2c\_slave} module are: +\begin{itemize} + \item simple operation + \begin{itemize} + \item passive until addressed by master + \item read transfers -- presents the user with the received byte at specific port + \item write transfer -- sends the byte at input port to the master + \item communication status can be checked via dedicated port + \end{itemize} + \item 7-bit addressing + \item standard (100~kHz) and fast (400~kHz) modes supported + \item no clock stretching, all information provided by the module should be handled + externally within the time span of an I$^2$C bit transfer + \item internal watchdog timer resets logic in case of bus error + \item architecture-independent, can be used with various FPGA types or ASICs +\end{itemize} + +%============================================================================== +% SEC: Instantiation +%============================================================================== +\section{Instantiation} +\label{sec:instantiation} + +This section offers information useful for instantiating the \textit{i2c\_slave} core module. +Table~\ref{tbl:ports} presents a list of ports of the \textit{i2c\_slave} module. + +I$^2$C-specific ports should be instantiated as outlined in Figure~\ref{fig:i2c-ports}, via +tri-state buffers enabled by the \textit{scl\_en\_o} lines \textit{sda\_en\_o}. + +\begin{figure}[h] + \centerline{\includegraphics[width=.75\textwidth]{fig/i2c-ports}} + \caption{Connecting the I$^2$C ports} + \label{fig:i2c-ports} +\end{figure} + +To instantiate a tri-state buffer in VHDL: + +\footnotesize +\begin{verbatim} + SCL <= scl_o when (scl_en_o = '1') else + 'Z'; + scl_i <= SCL; + + SDA <= sda_o when (sda_en_o = '1') else + 'Z'; + sda_i <= SDA; +\end{verbatim} + +\normalsize +\noindent and in Verilog: + +\footnotesize +\begin{verbatim} + assign SCL = (scl_en_o) ? scl_o : 1'bz; + assign scl_i = SCL; + assign SDA = (sda_en_o) ? sda_o : 1'bz; + assign sda_i = SDA; +\end{verbatim} + +\normalsize + +The rest of the ports should be connected in a normal manner to an external controlling module. A +component declaration of the \textit{i2c\_slave} module is readily available in the +\textit{i2c\_slave\_pkg.vhd} package file. The package also defines constants for the +statuses readable at the \textit{stat\_o} pin. Refer to Section~\ref{sec:oper} for details +regarding the various statuses. + +\begin{table}[h] + \caption{Ports of \textit{i2c\_slave} module} + \label{tbl:ports} + \centerline + { + \begin{tabular}{l c p{.65\textwidth}} + \hline + \multicolumn{1}{c}{\textbf{Name}} & \textbf{Size} & \multicolumn{1}{c}{\textbf{Description}} \\ + \hline + clk\_i & 1 & Clock input \\ + rst\_n\_i & 1 & Active-low reset input \\ + scl\_i & 1 & SCL line input \\ + scl\_o & 1 & SCL line output \\ + scl\_en\_o & 1 & SCL line tri-state enable \\ + sda\_i & 1 & SDA line input \\ + sda\_o & 1 & SDA line output \\ + sda\_en\_o & 1 & SDA line output tri-state enable \\ + i2c\_addr\_i & 7 & I$^2$C slave address of the module, compaired against received address \\ + ack\_n\_i & 1 & ACK to be sent to the master in case of master write transfers \\ + op\_o & 1 & State of the R/W bit at the end of the address byte \\ + tx\_byte\_i & 8 & Byte of data to be sent over I$^2$C \\ + rx\_byte\_o & 8 & Byte received over I$^2$C \\ + done\_p\_o & 1 & One \textit{clk\_i} cycle-wide pulse, signaling the slave module + has performed a valid transfer \\ + stat\_o & 3 & Current state of communication \\ + \hline + \end{tabular} + } +\end{table} + +%============================================================================== +% SEC: I2C bus +%============================================================================== +\section{I$^2$C Bus Protocol} +The I$^2$C bus protocol is a two-wire protocol defined by Philips/NXP. The original +specification \cite{i2c-spec} defines all aspects of the protocol, from hardware +connections on the bus, to bit- and byte-level data transfers and electrical +characteristics of the bus. A summary of the protocol is given here. + +\begin{figure}[h] + \centerline{\includegraphics[width=\textwidth]{fig/i2c-bus}} + \caption{I$^2$C bus topology} + \label{fig:i2c-bus} +\end{figure} + +Devices on the I$^2$C bus are connected together via two pins on the bus: the SCL +(serial clock) and SDA (serial data) pins. I$^2$C masters drive the SCL line to send or +receive bits on the SDA line. Both the SCL and SDA lines on an I$^2$C device are open-collector +pins; as Figure~\ref{fig:i2c-bus} shows, one pull-up resistor on the bus connects the line to +VCC and I$^2$C devices connect the SCL and SDA lines to ground when they drive the lines. +In this way, a device can set a logic low level on the bus by driving the pin and a logic +high level by releasing the pin. + +A typical I$^2$C bit-level transfer (Figure~\ref{fig:i2c-bitlevel}) follows the following sequence: +\begin{itemize} + \item master sends a start condition, driving the SDA line low while the SCL line is high + \item master issues a series of SCL pulses to a slave to read or write bits; + the SDA line must be stable for the duration of SCL high pulse for the bit to be properly + transferred + \item master sends a stop condition by releasing the SDA line while SCL line is high, + or a repeated start (similar to start) condition if it wants to continue data transfer +\end{itemize} + +\begin{figure}[h] + \centerline{\includegraphics[width=\textwidth]{fig/i2c-bitlevel}} + \caption{Bit-level transfers on the I$^2$C bus} + \label{fig:i2c-bitlevel} +\end{figure} + +Data are transferred on the bus in bytes, one bit at a time starting with the most significant bit. +After each sent byte, the other communicating party ACKs~('0') or NACKs~('1') the transfer on a +9$^{th}$ SCL cycle. Any number of bytes can be sent during a transfer, the master decides when data +transfer should stop by sending the stop condition. The folowing steps comprise a complete I$^2$C +data transfer (Figure~\ref{fig:i2c-transf}): +\begin{itemize} + \item master sends start condition + \item master sends slave address (7 bits of address + one R/W bit) + \item if a slave with this address exists, it ACKs ('0') the master + \item based on the R/W bit ('0' for read from slave, '1' for write to slave), the master either + reads or writes a byte bit by bit from/to the slave + \item the receiver ACKs ('0') or NACKs ('1') the byte on the ninth SCL cycle + \item any number of bytes may be sent, each followed by an ACK or NACK from the receiver + \item \textbf{optional:} the master may (or may not) reverse data transfer by issuing a repeated start and sending the + slave address with the R/W bit flipped + \item \textbf{optional:} any number of bytes may be sent, each followed by an ACK or NACK from the receiver + \item the master ends data transfer by sending the stop condition +\end{itemize} + +\begin{figure} + \centerline{\includegraphics[width=\textwidth]{fig/i2c-transf}} + \caption{Bytes transferred on the I$^2$C bus} + \label{fig:i2c-transf} +\end{figure} + +%============================================================================== +% SEC: Operation +%============================================================================== +\pagebreak +\section{Operation} +\label{sec:oper} + +The \textit{i2c\_slave} waits for a start condition to be performed on the I$^2$C bus by a +master module. The address is shifted in and if it matches the slave address set via +the \textit{i2c\_addr\_i} input, the \textit{done\_p\_o} output is set for one \textit{clk\_i} +cycle and the \textit{stat\_o} output signals an address match. Based on the eighth +bit of the first I2C transfer byte, the module then starts shifting in or out each byte +in the transfer, setting the \textit{done\_p\_o} output for one clock cycle after each +received/sent byte. The \textit{stat\_o} output can be checked to see if the byte has been +sent/received correctly. + +When the cycle-wide \textit{done\_p\_o} output is high (after every successful transfer, or a +stop condition) the \textit{stat\_o} (possibly together with the \textit{op\_o}) output can be checked +to see the appropriate action to be taken. The various statuses possible at the +\textit{stat\_o} output are listed in Table~\ref{tbl:stat}. + +\begin{table}[h] + \caption{Statuses at the \textit{stat\_o} pin} + \label{tbl:stat} + \centerline + { + \begin{tabular}{c p{.65\textwidth}} + \hline + \multicolumn{1}{c}{\textbf{\textit{stat\_o}}} & \multicolumn{1}{c}{\textbf{Description}} \\ + \hline + 00 & Slave idle, waiting for start condition. This is the state upon startup and after the I$^2$C stop + condition is received \\ + 01 & Address sent by the master matches that at \textit{i2c\_addr\_i}; \textit{op\_o} + valid \\ + 10 & Read done, waiting for ACK/NACK to send to master \\ + 11 & Write done, waiting for next byte to send to master \\ + \hline + \end{tabular} + } +\end{table} + +The \textit{ack\_n\_i} port is used for sending the ACK to the master. The polarity of the bit +is that of the I$^2$C ACK signal ('0' -- ACK, '1' -- NACK). A '0' should be set +at the input also when the address is ACKed, otherwise the slave will not acknowledge its own +address. This implies that the \textit{ack\_n\_i} pin can be used to isolate the slave from the +bus. + +\subsection{Read mode} + +When the eighth bit of the address byte is low (R/W = '0'), the slave goes into read +mode. Each bit of the byte sent by the master is shifted in on the falling edge of SCL. After +eight bits have been shifted in, \textit{done\_p\_o} is set for one \textit{clk\_i} cycle and +the status signals a successful read ("10"). The received byte should be read from the +\textit{rx\_byte\_o} output and an ACK ('0') or NACK~('1') should be sent to the master via the +\textit{ack\_n\_i} pin. The \textit{i2c\_slave} module does not implement clock stretching, +so the \textit{ack\_n\_i} pin should be set before the SCL line goes high. + +The steps below should be followed when reading one or more bytes sent by the master: + +\begin{enumerate} + \item Wait for \textit{done\_p\_o} to go high, signaling the I$^2$C address of the slave + has been read. + \item Check that \textit{stat\_o} is "01" (address good) and that \textit{op\_o} is '0' + (master write, slave read). Set a '0' at the \textit{ack\_n\_i} input to send the + ACK to the address; if \textit{ack\_n\_i} is '1', the slave does not acknowledge its + own address. + \item Wait for \textit{done\_p\_o} to go high. + \item Check that \textit{stat\_o} is "10" (read done), read the received byte from + \textit{rx\_byte\_o} and write a '0' at \textit{ack\_n\_i} to send an ACK, or a + '1' to send an NACK. + \item The transfer is repeated until the master sends a stop condition. + \item After the stop condition is received, the \textit{done\_p\_o} goes high for one + clock cycle and the status is set to "00". +\end{enumerate} + +\subsection{Write mode} + +When a master reads from the slave, the eighth bit of the address byte is high +(R/W = '1'). In this case, the \textit{i2c\_slave} module goes in write mode, where +the byte at the \textit{tx\_byte\_i} port is sent to the master. When the byte has been +successfully sent, the \textit{done\_p\_o} is high for one clock cycle and the \textit{stat\_o} +port has the value "11", signaling the slave has successfully sent a byte and is +awaiting the loading of another byte. + +The steps below should be followed when writing one or more bytes to a master: + +\begin{enumerate} + \item Wait for \textit{done\_p\_o} to go high, signaling the I$^2$C address of the slave + has been read. + \item Check that \textit{stat\_o} is "01" (address good) and \textit{op\_o} is '1' + (master read, slave write). Set the byte to be sent to the master at the + \textit{tx\_byte\_i} input. Set a '0' at \textit{ack\_n\_i} to send the ACK to the address; + if \textit{ack\_n\_i} is '1', the slave does not acknowledge its own address. + \item Wait for \textit{done\_p\_o} to go high. + \item Check that \textit{stat\_o} is "11" (write done) and set the next byte to be + sent at the \textit{tx\_byte\_i} port. + \item If the master acknowledges the transfer, the next byte is sent, otherwise, the master + will send a stop condition, so the \textit{i2c\_slave} module is reset. +\end{enumerate} + +Note that if a stop condition is received from the master, the \textit{done\_p\_o} goes high for +one clock cycle and the status is set to "00". + +%============================================================================== +% SEC: Implementation +%============================================================================== +\section{Implementation} +\label{sec:implem} + +This section presents implementation details of the \textit{i2c\_slave} module. A simplified +block diagram of the module is presented in Figure~\ref{fig:i2c-slave-bd}. + +\begin{figure}[h] + \centerline{\includegraphics[width=\textwidth]{fig/i2c-slave-bd}} + \caption{Block diagram of \textit{i2c\_slave} module} + \label{fig:i2c-slave-bd} +\end{figure} + +Deglitched versions of the SCL and SDA lines control operation of the central finite-state +machine (FSM), which sets the outputs and controls the rest of the components in the module. + +The FSM is sensitive to start and stop conditions and falling edges of the SCL line. It +controls how outputs are set, when the reception and transmission shift registers (RXSR/TXSR) +are loaded and when they shift, and acknowledging to the address and bytes sent by the +master. Table~\ref{tbl:fsm} lists the states of the FSM and the operations performed +in each state. + +An internal watchdog counter is implemented inside the \textit{i2c\_slave} module. This counter +counts up to 1 second and is reset at the start of each state of the FSM. If the FSM stops +in one of the states because of a bus error, the watchdog resets the FSM, thereby stopping the +communication. + +\begin{longtable}{l p{.7\textwidth}} + \caption{The states of the \textit{i2c\_slave} FSM} + \label{tbl:fsm} \\ + + \hline + \multicolumn{1}{c}{\textbf{State}} & \multicolumn{1}{c}{\textbf{Description}} \\ + \hline + \endfirsthead + + \hline + \multicolumn{1}{c}{\textbf{State}} & \multicolumn{1}{c}{\textbf{Description}} \\ + \hline + \endhead + + \hline + \endfoot + + \textit{IDLE} & Idle state, FSM default state after reset and the state returned to after + reception of a stop condition. \\ + \textit{STA} & State reached after a start condition is received. On the falling edge + of SCL, the FSM transitions to \textit{ADDR} state. \\ + \textit{ADDR} & Shift in 7 address bits and R/W bit and go to \textit{ADDR\_ACK} + state. Each bit is shifted in on the falling edge of SCL. If the + received address matches, \textit{op\_o} and \textit{done\_p\_o} are set. \\ + \textit{ADDR\_ACK} & Check received address and send the ACK value at \textit{ack\_n\_i} if + the address corresponds to \textit{i2c\_addr\_i}. If the R/W bit is high, + go to \textit{RD} state, otherwise go to \textit{WR\_LOAD\_TXSR} state. + If received address does not match, NACK and go to \textit{IDLE} + state. \\ + \textit{RD} & Shift in eight bits sent by master and go to \textit{RD\_ACK} state. Each bit + is shifted in on the falling edge of SCL. When eight bits have been shifted in, + set \textit{done\_p\_o}. \\ + \textit{RD\_ACK} & Read \textit{ack\_n\_i} and forward it to \textit{sda\_o} (ACK/NACK + from external controller). If \textit{ack\_n\_i} is '0', then go back to + \textit{RD} state, else to \textit{IDLE} state. \\ + \textit{WR\_LOAD\_TXSR} & Load TX shift register with data at \textit{tx\_byte\_i} input + and go to \textit{WR} state. \\ + \textit{WR} & Shift out the eight bits of the TXSR starting with MSB and go to + \textit{WR\_ACK} state. TXSR shifts left on falling edge of SCL. When + eight bits have been shifted out, \textit{done\_p\_o} is set.\\ + \textit{WR\_ACK} & Read ACK bit sent by master. If '0', go back to \textit{WR} state, otherwise + go to \textit{IDLE} state. \\ +\end{longtable} + + +%\pagebreak +%\begin{table}[h] +% \caption{The states of the \textit{i2c\_slave} FSM} +% \label{tbl:fsm} +% \centerline +% { +% \begin{tabular}{l p{.7\textwidth}} +% \hline +% \multicolumn{1}{c}{\textbf{State}} & \multicolumn{1}{c}{\textbf{Description}} \\ +% \hline +% \textit{IDLE} & Idle state, FSM default state after reset and the state returned to after +% reception of a stop condition. \\ +% \textit{STA} & State reached after a start condition is received. On the falling edge +% of SCL, the FSM transitions to \textit{ADDR} state. \\ +% \textit{ADDR} & Shift in 7 address bits and R/W bit and go to \textit{ADDR\_ACK} +% state. Each bit is shifted in on the falling edge of SCL. If the +% received address matches, \textit{op\_o} and \textit{done\_p\_o} are set. \\ +% \textit{ADDR\_ACK} & Check received address and send the ACK value at \textit{ack\_n\_i} if +% the address corresponds to \textit{i2c\_addr\_i}. If the R/W bit is high, +% go to \textit{RD} state, otherwise go to \textit{WR\_LOAD\_TXSR} state. +% If received address does not match, NACK and go to \textit{IDLE} +% state. \\ +% \textit{RD} & Shift in eight bits sent by master and go to \textit{RD\_ACK} state. Each bit +% is shifted in on the falling edge of SCL. When eight bits have been shifted in, +% set \textit{done\_p\_o}. \\ +% \textit{RD\_ACK} & Read \textit{ack\_n\_i} and forward it to \textit{sda\_o} (ACK/NACK +% from external controller). If \textit{ack\_n\_i} is '0', then go back to +% \textit{RD} state, else to \textit{IDLE} state. \\ +% \textit{WR\_LOAD\_TXSR} & Load TX shift register with data at \textit{tx\_byte\_i} input +% and go to \textit{WR} state. \\ +% \textit{WR} & Shift out the eight bits of the TXSR starting with MSB and go to +% \textit{WR\_ACK} state. TXSR shifts left on falling edge of SCL. When +% eight bits have been shifted out, \textit{done\_p\_o} is set.\\ +% \textit{WR\_ACK} & Read ACK bit sent by master. If '0', go back to \textit{WR} state, otherwise +% go to \textit{IDLE} state. \\ +% \hline +% \end{tabular} +% } +%\end{table} + +%============================================================================== +% Bibliography +%============================================================================== +\pagebreak +\bibliographystyle{ieeetr} +\bibliography{gc_i2c_slave} + +\end{document} diff --git a/doc/wb_i2c_bridge/Makefile b/doc/wb_i2c_bridge/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..202f8de9e1b8fe81aae8303b0265fa7abac1930f --- /dev/null +++ b/doc/wb_i2c_bridge/Makefile @@ -0,0 +1,14 @@ +FILE=wb_i2c_bridge + +all: + $(MAKE) -C fig + pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex + bibtex $(FILE).aux + pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex + pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex + evince $(FILE).pdf & + +clean: + $(MAKE) -C fig clean + rm -rf *.aux *.dvi *.log $(FILE).pdf *.lof *.lot *.out *.toc *.bbl *.blg *.gz + diff --git a/doc/wb_i2c_bridge/README.txt b/doc/wb_i2c_bridge/README.txt new file mode 100644 index 0000000000000000000000000000000000000000..e69d1177f1e40e729e63801d1f69fcf7653bf564 --- /dev/null +++ b/doc/wb_i2c_bridge/README.txt @@ -0,0 +1,4 @@ +Type 'make' to create your .pdf documentation file. + +You need Inkscape to make the documentation files: +sudo apt-get install inkscape \ No newline at end of file diff --git a/doc/wb_i2c_bridge/cern-title.tex b/doc/wb_i2c_bridge/cern-title.tex new file mode 100644 index 0000000000000000000000000000000000000000..9f132cb1d224ad3393a7c4b6d78547ad006323da --- /dev/null +++ b/doc/wb_i2c_bridge/cern-title.tex @@ -0,0 +1,31 @@ +\begin{titlepage} + +\vspace*{3cm} + +%--------------------------------------------------------------- +% title +%--------------------------------------------------------------- +\noindent{\LARGE \textbf{VBCP to Wishbone bridge}} + +\noindent \rule{\textwidth}{.1cm} + +\hfill\today + +\vspace*{3cm} + +\begin{figure}[h] + \includegraphics[height=3cm]{fig/cern-logo} + \hfill + \includegraphics[height=3cm]{fig/ohwr-logo} +\end{figure} + +\vfill + +%--------------------------------------------------------------- +% name +%--------------------------------------------------------------- +\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}} + +\noindent \rule{\textwidth}{.05cm} + +\end{titlepage} diff --git a/doc/wb_i2c_bridge/fig/Makefile b/doc/wb_i2c_bridge/fig/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..00fe82ab1dec0a92d0f8fbd96f7690b50f105166 --- /dev/null +++ b/doc/wb_i2c_bridge/fig/Makefile @@ -0,0 +1,11 @@ +SRC = $(wildcard *.svg) +OBJS = $(SRC:.svg=.pdf) + +all: $(OBJS) + echo $(OBJS) + +%.pdf : %.svg + inkscape -f $< -A $@ + +clean : + rm -f *.pdf diff --git a/doc/wb_i2c_bridge/fig/cern-logo.svg b/doc/wb_i2c_bridge/fig/cern-logo.svg new file mode 100644 index 0000000000000000000000000000000000000000..470c7b0a157435f6443c68c4dd45248e68624585 --- /dev/null +++ b/doc/wb_i2c_bridge/fig/cern-logo.svg @@ -0,0 +1,53 @@ +<?xml version="1.0" encoding="utf-8"?> +<!-- Generator: Adobe Illustrator 15.0.2, SVG Export Plug-In . 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transform="translate(202.75875,-34.98513)" + id="g3859"> + <path + transform="matrix(0.60235134,0,0,0.18100198,258.57758,384.96948)" + d="m 331.42857,225.21933 c 0,59.17337 -51.16746,107.14286 -114.28572,107.14286 -63.11825,0 -114.28571,-47.96949 -114.28571,-107.14286 0,-59.17337 51.16746,-107.14286 114.28571,-107.14286 63.11826,0 114.28572,47.96949 114.28572,107.14286 z" + sodipodi:ry="107.14286" + sodipodi:rx="114.28571" + sodipodi:cy="225.21933" + sodipodi:cx="217.14285" + id="path3847" + style="fill:#e5e5e5;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:3.02854061;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0" + sodipodi:type="arc" /> + <text + xml:space="preserve" + style="font-size:10px;font-style:normal;font-weight:normal;text-align:center;line-height:125%;letter-spacing:0px;word-spacing:0px;text-anchor:middle;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans" + x="389.11264" + y="428.26636" + id="text3849" + sodipodi:linespacing="125%"><tspan + sodipodi:role="line" + id="tspan3851" + x="389.11264" + y="428.26636" + style="font-weight:bold">SYSMON_RD</tspan></text> + </g> + <g + transform="translate(27.749824,-111.75672)" + id="g3874"> + <path + sodipodi:type="arc" + style="fill:#e5e5e5;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:3.02854061;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0" + id="path3853" + sodipodi:cx="217.14285" + sodipodi:cy="225.21933" + sodipodi:rx="114.28571" + sodipodi:ry="107.14286" + d="m 331.42857,225.21933 c 0,59.17337 -51.16746,107.14286 -114.28572,107.14286 -63.11825,0 -114.28571,-47.96949 -114.28571,-107.14286 0,-59.17337 51.16746,-107.14286 114.28571,-107.14286 63.11826,0 114.28572,47.96949 114.28572,107.14286 z" + transform="matrix(0.60235134,0,0,0.18100198,433.58651,384.96948)" /> + <text + sodipodi:linespacing="125%" + id="text3855" + y="428.26636" + x="564.12158" + style="font-size:10px;font-style:normal;font-weight:normal;text-align:center;line-height:125%;letter-spacing:0px;word-spacing:0px;text-anchor:middle;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans" + xml:space="preserve"><tspan + style="font-weight:bold" + y="428.26636" + x="564.12158" + id="tspan3857" + sodipodi:role="line">SYSMON_RD_WB</tspan></text> + </g> + <path + style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-start:none;marker-end:url(#TriangleOutM)" + d="m 139.52732,132.23948 c -26.4953,-21.09124 -25.87961,32.36778 -4.92449,16.66752" + id="path3898" + inkscape:connector-curvature="0" + sodipodi:nodetypes="cc" /> + <path + style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#TriangleOutM)" + d="m 200.44643,136.38004 c 4.11665,-8.10283 40.9024,-11.03375 62.28111,-2.02294" + id="path4524" + inkscape:connector-curvature="0" + sodipodi:nodetypes="cc" /> + <path + sodipodi:nodetypes="cc" + inkscape:connector-curvature="0" + id="path4708" + d="m 337.43634,121.15915 c 5.74493,-22.771691 -47.66802,-18.57238 -42.07827,-2.70932" + style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-start:none;marker-end:url(#TriangleOutM)" /> + <text + xml:space="preserve" + style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans" + x="80.46682" + y="141.33536" + id="text4712" + sodipodi:linespacing="125%"><tspan + sodipodi:role="line" + id="tspan4714" + x="80.46682" + y="141.33536" + style="font-size:8px">done='0'</tspan></text> + <text + sodipodi:linespacing="125%" + id="text4716" + y="123.73908" + x="221.63564" + style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans" + xml:space="preserve"><tspan + style="font-size:8px" + y="123.73908" + x="221.63564" + id="tspan4718" + sodipodi:role="line">done='1'</tspan></text> + <text + xml:space="preserve" + style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans" + x="273.39542" + y="101.91621" + id="text4720" + sodipodi:linespacing="125%"><tspan + sodipodi:role="line" + id="tspan4722" + x="273.39542" + y="101.91621" + style="font-size:8px">adr_byte_cnt < 1</tspan></text> + <path + sodipodi:nodetypes="cc" + inkscape:connector-curvature="0" + id="path4724" + d="m 365.04288,129.81405 c 4.11665,-8.10283 47.8472,-18.35736 64.30141,-2.52802" + style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#TriangleOutM)" /> + <text + sodipodi:linespacing="125%" + id="text4726" + y="114.77335" + x="360.89542" + style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans" + xml:space="preserve"><tspan + style="font-size:8px" + y="114.77335" + x="360.89542" + id="tspan4728" + sodipodi:role="line">adr_byte_cnt = 1</tspan></text> + <path + style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#TriangleOutM)" + d="m 439.01786,150.30861 c -77.47925,35.22605 -156.57043,39.01946 -237.85714,0" + id="path4730" + inkscape:connector-curvature="0" + sodipodi:nodetypes="cc" /> + <text + xml:space="preserve" + style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans" + x="295.39087" + y="172.85713" + id="text4914" + sodipodi:linespacing="125%"><tspan + sodipodi:role="line" + id="tspan4916" + x="295.39087" + y="172.85713" + style="font-size:8px">wb_err = '1'</tspan></text> + <path + style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#TriangleOutM)" + d="m 516.79686,157.59305 c 4.24722,16.83309 5.34307,32.28235 0.50508,51.97698" + id="path4934" + inkscape:connector-curvature="0" + sodipodi:nodetypes="cc" /> + <text + sodipodi:linespacing="125%" + id="text5118" + y="183.92856" + x="525.39087" + style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans" + xml:space="preserve"><tspan + style="font-size:8px" + y="183.92856" + x="525.39087" + id="tspan5120" + sodipodi:role="line">wb_ack = '1'</tspan></text> + <path + style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-start:none;marker-end:url(#TriangleOutM)" + d="m 474.01408,236.41146 c -22.92817,10.26093 -30.01763,33.25019 -31.92314,56.77732" + id="path5122" + inkscape:connector-curvature="0" + sodipodi:nodetypes="cc" /> + <path + sodipodi:nodetypes="cc" + inkscape:connector-curvature="0" + id="path5488" + d="m 531.24885,231.71784 c 15.60456,17.83707 24.20925,38.30095 26.11476,61.82808" + style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-start:none;marker-end:url(#TriangleOutM)" /> + <text + xml:space="preserve" + style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans" + x="386.4949" + y="260.70016" + id="text5490" + sodipodi:linespacing="125%"><tspan + sodipodi:role="line" + id="tspan5492" + x="386.4949" + y="260.70016" + style="font-size:8px">op = start_op</tspan></text> + <text + sodipodi:linespacing="125%" + id="text5494" + y="260.70016" + x="553.17004" + style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans" + xml:space="preserve"><tspan + style="font-size:8px" + y="260.70016" + x="553.17004" + id="tspan5496" + sodipodi:role="line">op /= start_op</tspan></text> + <path + sodipodi:nodetypes="cc" + inkscape:connector-curvature="0" + id="path5498" + d="m 350.14413,305.98572 c -20.49584,-21.97663 -28.48815,28.97799 -4.92449,16.66752" + style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-start:none;marker-end:url(#TriangleOutM)" /> + <path + style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-start:none;marker-end:url(#TriangleOutM)" + d="m 657.50816,384.37858 c 16.74584,-21.61949 24.91673,27.72799 1.35307,15.41752" + id="path5500" + inkscape:connector-curvature="0" + sodipodi:nodetypes="cc" /> + <text + sodipodi:linespacing="125%" + id="text5502" + y="315.34302" + x="276.4949" + style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans" + xml:space="preserve"><tspan + style="font-size:8px" + y="315.34302" + x="276.4949" + id="tspan5504" + sodipodi:role="line">byte_cnt < 3</tspan></text> + <text + xml:space="preserve" + style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans" + x="677.19373" + y="390.0943" + id="text5506" + sodipodi:linespacing="125%"><tspan + sodipodi:role="line" + id="tspan5508" + x="677.19373" + y="390.0943" + style="font-size:8px">byte_cnt < 3</tspan></text> + <path + style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#TriangleOutM)" + d="m 413.58815,333.34433 0,34.55357" + id="path5510" + inkscape:connector-curvature="0" + sodipodi:nodetypes="cc" /> + <path + sodipodi:nodetypes="cc" + inkscape:connector-curvature="0" + id="path5694" + d="m 595.41561,333.34433 0,34.55357" + style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#TriangleOutM)" /> + <text + xml:space="preserve" + style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans" + x="360.84262" + y="352.21359" + id="text5696" + sodipodi:linespacing="125%"><tspan + sodipodi:role="line" + id="tspan5698" + x="360.84262" + y="352.21359" + style="font-size:8px">byte_cnt = 3</tspan></text> + <text + sodipodi:linespacing="125%" + id="text5884" + y="429.46619" + x="382.80508" + style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans" + xml:space="preserve"><tspan + style="font-size:8px;text-align:center;text-anchor:middle" + y="429.46619" + x="382.80508" + sodipodi:role="line" + id="tspan5888">I<tspan + style="font-size:65.00091553%;text-align:center;text-anchor:middle;baseline-shift:super" + id="tspan4982">2</tspan>C stop condition</tspan><tspan + style="font-size:8px;text-align:center;text-anchor:middle" + y="439.46619" + x="382.80508" + sodipodi:role="line" + id="tspan4978"><tspan + style="font-style:italic;text-align:center;text-anchor:middle" + id="tspan4980">or </tspan>wb_err</tspan></text> + <text + xml:space="preserve" + style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans" + x="600.64722" + y="351.1088" + id="text5896" + sodipodi:linespacing="125%"><tspan + sodipodi:role="line" + id="tspan5898" + x="600.64722" + y="351.1088" + style="font-size:8px">wb_ack = '1'</tspan></text> + <text + sodipodi:linespacing="125%" + id="text6084" + y="433.26578" + x="587.95544" + style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans" + xml:space="preserve"><tspan + style="font-size:8px" + y="433.26578" + x="587.95544" + id="tspan6086" + sodipodi:role="line">byte_cnt = 3</tspan></text> + <g + id="g6088" + transform="translate(341.93664,317.47761)"> + <g + id="g6096"> + <g + id="g6101" + transform="translate(-10.53609,0)"> + <path + sodipodi:type="arc" + style="fill:#e5e5e5;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:4.80641747;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:28.83850474, 28.83850474;stroke-dashoffset:0" + id="path6090" + sodipodi:cx="217.14285" + sodipodi:cy="225.21933" + sodipodi:rx="114.28571" + sodipodi:ry="107.14286" + d="m 331.42857,225.21933 c 0,59.17337 -51.16746,107.14286 -114.28572,107.14286 -63.11825,0 -114.28571,-47.96949 -114.28571,-107.14286 0,-59.17337 51.16746,-107.14286 114.28571,-107.14286 63.11826,0 114.28572,47.96949 114.28572,107.14286 z" + transform="matrix(0.29285112,0,0,0.14781215,104.81247,95.08144)" /> + <text + xml:space="preserve" + style="font-size:10px;font-style:normal;font-weight:normal;text-align:center;line-height:125%;letter-spacing:0px;word-spacing:0px;text-anchor:middle;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans" + x="168.41277" + y="130.90334" + id="text6092" + sodipodi:linespacing="125%"><tspan + sodipodi:role="line" + id="tspan6094" + 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a/doc/wb_i2c_bridge/wb_i2c_bridge.tex b/doc/wb_i2c_bridge/wb_i2c_bridge.tex new file mode 100644 index 0000000000000000000000000000000000000000..37af4dc1eb530044ee68b5b166fe071ba61dcb52 --- /dev/null +++ b/doc/wb_i2c_bridge/wb_i2c_bridge.tex @@ -0,0 +1,459 @@ +%============================================================================== +% Document header +%============================================================================== +\documentclass[a4paper,11pt]{article} + +% Color package +\usepackage[usenames,dvipsnames]{color} + +% Hyperrefs +\usepackage[ + colorlinks = true, + linkcolor = Mahogany, + citecolor = Mahogany, + urlcolor = blue, +]{hyperref} + +\usepackage{graphicx} +\usepackage{multirow} + + +\usepackage[toc,page]{appendix} + +% Header and footer customization +\usepackage{fancyhdr} +\setlength{\headheight}{15.2pt} +\pagestyle{fancy} +\fancyhead[L]{\nouppercase{\leftmark}} +\fancyhead[R]{} +\renewcommand{\footrulewidth}{0.4pt} + +%============================================================================== +% Start of document +%============================================================================== +\begin{document} + +%------------------------------------------------------------------------------ +% Title +%------------------------------------------------------------------------------ +\include{cern-title} + +%------------------------------------------------------------------------------ +% Revision history +%------------------------------------------------------------------------------ +\thispagestyle{empty} +\section*{Revision history} + +\centerline +{ + \begin{tabular}{l c p{.6\textwidth}} + \hline + \multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\ + \hline + 26-06-2013 & 0.01 & First draft \\ + 14-08-2013 & 0.02 & Second draft \\ + 22-10-2013 & 0.03 & Added \textit{Access commands} section, updated document according to + changes in protocol \\ + 29-10-2013 & 0.04 & Changed PDF link colors \\ + \hline + \end{tabular} +} + +\pagebreak +\pagenumbering{roman} +\setcounter{page}{1} +\tableofcontents + +%------------------------------------------------------------------------------ +% List of figs, tables, abbrevs +%------------------------------------------------------------------------------ +\pagebreak +\listoffigures +\listoftables + +\section*{List of Abbreviations} +\begin{tabular}{l l} + FSM & Finite-State Machine \\ + VBCP & Inter-Integrated Circuit (bus) \\ + SysMon & ELMA crate System Monitor board \\ + VME & VERSAmodule Eurocard \\ +\end{tabular} + +\pagebreak +\pagenumbering{arabic} +\setcounter{page}{1} + +%============================================================================== +% SEC: Intro +%============================================================================== +\section{Introduction} +\label{sec:intro} + +This document describes the \textit{vbcp\_wb} module, a VME Board Control Protocol (VBCP) to Wishbone +bridge HDL core for VME64x crates from ELMA. These crates offer the possibility of accessing +boards in VME slots via either VME, or VBCP. Boards not using the VME lines +on a slot can implement the \textit{vbcp\_wb} module on an FPGA; implements an +VBCP slave and translates VBCP accesses into Wishbone \cite{wb-spec} accesses to a +Wishbone slave device. + +A typical system where the \textit{vbcp\_wb} module is employed is shown in +Figure~\ref{fig:sys}. ELMA VME crates contain a SysMon (system monitor) board~\cite{sysmon}, +that is mainly used for monitoring VME voltages and controlling the fans of the VME crate. +The SysMon can be connected to via either a serial connection or Telnet. Then, sending +specific commands (see Section \ref{sec:testing}) via one of the two are translated by the +SysMon into VBCP accesses following the protocol described in Section~\ref{sec:vbcp}. + +\begin{figure}[h] + \centerline{\includegraphics[width=\textwidth]{fig/sys}} + \caption{Typical system for the \textit{vbcp\_wb} module} + \label{fig:sys} +\end{figure} + +%============================================================================== +% SEC: Instantiation +%============================================================================== +\section{Instantiation} +\label{sec:instantiation} + +The ports of the \textit{vbcp\_wb} module are shown in Table~\ref{tbl:ports}. +The I$^2$C signals should be connected to tri-state ports, as shown in +Figure~\ref{fig:i2c-ports}; Wishbone slaves should be connected to the +Wishbone master interface ports, prefixed with \textit{wbm}. + +\begin{table}[h] + \caption{Ports of \textit{vbcp\_wb} module} + \label{tbl:ports} + \centerline + { + \begin{tabular}{l c p{.6\textwidth}} + \hline + \multicolumn{1}{c}{\textbf{Port}} & \textbf{Size} & \multicolumn{1}{c}{\textbf{Description}} \\ + \hline + clk\_i & 1 & Clock input \\ + rst\_n\_i & 1 & Active-low reset input \\ + sda\_en\_o & 1 & SDA line output tri-state enable \\ + sda\_i & 1 & SDA line input \\ + sda\_o & 1 & SDA line output \\ + scl\_en\_o & 1 & SCL line tri-state enable \\ + scl\_i & 1 & SCL line input \\ + scl\_o & 1 & SCL line output \\ + i2c\_addr\_i & 7 & VBCP slave address on ELMA VBCP bus \\ + tip\_o & 1 & Transfer In Progress \newline + '1' -- I$^2$C address sent by SysMon matches that of the VBCP slave \newline + '0' -- after transfer has completed and VBCP slave is idle \\ + err\_o & 1 & Error bit, high for one \textit{clk\_i} cycle when the Wishbone address + the SysMon tries to access is invalid \\ + wbm\_stb\_o & 1 & Wishbone data strobe output \\ + wbm\_cyc\_o & 1 & Wishbone valid cycle output \\ + wbm\_sel\_o & 4 & Wishbone byte select output \\ + wbm\_we\_o & 1 & Wishbone write enable output \\ + wbm\_dat\_i & 32 & Wishbone data input (to master) \\ + wbm\_dat\_o & 32 & Wishbone data output (from master) \\ + wbm\_adr\_o & 32 & Wishbone address output \\ + wbm\_ack\_i & 1 & Wishbone acknowledge signal input \\ + wbm\_rty\_i & 1 & Wishbone retry signal input \\ + wbm\_err\_i & 1 & Wishbone error signal input \\ + \hline + \end{tabular} + } +\end{table} + +\begin{figure}[h] + \centerline{\includegraphics[width=.75\textwidth]{fig/i2c-ports}} + \caption{VBCP port external connections} + \label{fig:i2c-ports} +\end{figure} + +%\begin{table}[h] +% \caption{Wishbone datasheet of \textit{vbcp\_wb} module} +% \label{tbl:wb-ds} +% \centerline +% { +% \begin{tabular}{p{.4\textwidth} p{.43\textwidth}} +% \hline +% \multicolumn{1}{c}{\textbf{Description}} & \multicolumn{1}{c}{\textbf{Specification}} \\ +% \hline +% General description & ELMA VBCP to Wishbone bridge \\ +% Supported cycles & Master, read/write \\ +% Data port, size & 32-bit \\ +% Data port, granularity & 32-bit \\ +% Data port, max. operand size & 32-bit \\ +% Data transfer ordering & Little-endian \\ +% Data transfer sequencing & Undefined \\ +% Supported signal list and +% cross-reference to equivalent +% Wishbone signals & wbm\_stb\_o -- STB\_O \newline +% wbm\_cyc\_o -- CYC\_O \newline +% wbm\_sel\_o -- SEL\_O \newline +% wbm\_we\_o -- WE\_O \newline +% wbm\_dat\_i -- DAT\_I \newline +% wbm\_dat\_o -- DAT\_O \newline +% wbm\_adr\_o -- ADR\_O \newline +% wbm\_ack\_i -- ACK\_I \newline +% wbm\_rty\_i -- RTY\_I \newline +% wbm\_err\_i -- ERR\_I \\ +% ERR\_I signal behaviour & i2c\_err\_o set \\ +% \hline +% \end{tabular} +% } +%\end{table} + +%============================================================================== +% SEC: Testing +%============================================================================== +\section{Testing the \textit{vbcp\_wb} module} +\label{sec:testing} + +After proper synthesis and download to the FPGA, a Telnet or serial connection +should be made to the SysMon board. Commands can then be sent to the boards via +the SysMon. The two commands relevant for this basic test are \textit{readreg} +and \textit{writereg}. These and other commands relevant for accessing board +registers are outlined in Section~\ref{sec:vbcp-cmds}. + +The example below shows how to connect to an ELMA crate at IP address 1.2.3.4, +obtaining the value of a register at address 0x10 in a board in VME slot 2, +writing the hex value 0x1234 to the same register and reading it back to check for +proper modification. + +\pagebreak +\begin{verbatim} +$ telnet 1.2.3.4 +Trying 1.2.3.4... +Connected to 1.2.3.4. +Escape character is '^]'. +login:user +password:********** +%>readreg 2 10 + Read Data: 00ABCDEF +%>writereg 2 10 1234 + Done! +%>readreg 2 10 + Read Data: 00001234 +\end{verbatim} + +%============================================================================== +% SEC: Protocol +%============================================================================== +\section{The VME Board Control Protocol} +\label{sec:vbcp} + +%------------------------------------------------------------------------------ +\subsection{Protocol details} +\label{sec:vbcp-prot} + +The VME backplane provides two serial lines (\textit{SERCLK} and \textit{SERDAT}) +on the P1 connector. These lines can be used to access boards placed in a VME +slots to control them, in cases where the VME interface is not implemented. + +The VME Board Control Protocol (VBCP)~\cite{sysmon-i2c} has been defined for such +purposes. Using I$^2$C as a low-level protocol, the bytes of a register can be read +from or written to a VME board. + +Figure~\ref{fig:sysmon-wr} shows a write operation from the SysMon to a VME +board. The process starts with the control byte, containing the board's +I$^2$C slave address and the read/write bit cleared, indicating an +I$^2$C write. After the slave's ACK, the following two bytes send the +12-bit register address in little-endian order (most significant byte first). +After the address has been acknowledged, the following four I$^2$C transfers +are used to transmit the 32-bit data to be written to the board register. +Data transmission occurs in big-endian order (least significant byte first). + +\begin{figure}[h] + \centerline{\includegraphics[width=.9\textwidth]{fig/sysmon-wr}} + \caption{SysMon write operation} + \label{fig:sysmon-wr} +\end{figure} + +\begin{figure}[h] + \centerline{\includegraphics[width=\textwidth]{fig/sysmon-rd}} + \caption{SysMon read operation} + \label{fig:sysmon-rd} +\end{figure} + +A read transfer (Figure~\ref{fig:sysmon-rd}) from a VME board is similar +to the write transfer. The differences lie in the retransmission of the +control byte after the register address, this time with the read/write +bit set, to indicate an I$^2$C read. Following the ACK from the slave, +the transfer direction changes and the SysMon will read the four data +bytes sent by the VME board. As with the write transfer, the data bytes +are sent by the VME board in big-endian order. + +%------------------------------------------------------------------------------ +\subsection{Access commands} +\label{sec:vbcp-cmds} + +In order to send data to a VME board using VBCP, a user connects to the SysMon +via Telnet and sends commands which the SysMon translates into I$^2$C accesses +as outlined in the previous section. The commands supported by the \textit{vbcp\_wb} +module are shown in Table~\ref{tbl:cmds}. + +\begin{table}[h] + \caption{The \textit{readreg} and \textit{writereg} commands} + \label{tbl:cmds} + \centerline + { + \begin{tabular}{l p{.6\textwidth}} + \hline + \multicolumn{1}{c}{\textbf{Command}} & \multicolumn{1}{c}{\textbf{Description}} \\ + \hline + writereg \textit{slot addr val} & Writes the \textit{hex} value \textit{val} to hex address + \textit{addr} of board in slot number \textit{slot} \\ + writemregs \textit{slot addr v1 .. v8} & This command is similar to the \textit{writereg} + command, but it allows writing up to eight different values + to the same Wishbone register. The values are given in hexadecimal + format and are separate by spaces \\ + readreg \textit{slot addr} & Returns the value of register at hex address \textit{addr} of + board in slot number \textit{slot} \\ + \hline + \end{tabular} + } +\end{table} + +One noteworthy subject here is the \textit{writemregs} command. This command allows +writing more up to eight words to the same Wishbone register. It is useful +when one wants to use a Wishbone register as a proxy for accessing an on-board +peripheral where large amounts of data are to be written. An external memory is a +good example of such a peripheral. + +\begin{figure} + \centerline{\includegraphics[width=\textwidth]{fig/writemregs}} + \caption{SysMon write using \textit{writemregs}} + \label{fig:writemregs} +\end{figure} + +In principle, the \textit{writemregs} is a \textit{writereg} with multiple data words +packed together, as outlined in Figure~\ref{fig:writemregs}. In this figure, each data word +is split in four bytes as outlined in Figure~\ref{fig:sysmon-wr}, with an ACK sent by +the VME board after every byte. + +As Figure~\ref{fig:writemregs} shows, the data words are sent in little-endian order, +word 0 is sent first, followed by word 1 and so forth, until word 7. + +%============================================================================== +% SEC: Implem +%============================================================================== +\section{Implementation} +\label{sec:implem} + +In order to perform low-level I$^2$C transfers, the \textit{i2c\_slave} module +is instantiated and used within the \textit{vbcp\_wb} +module. The outputs of the \textit{i2c\_slave} module are used as controls +for an eight-state finite state machine (FSM), a simplified version of which +is shown in Figure~\ref{fig:fsm}. Table~\ref{tbl:fsm} also lists the states of +the state machine. + +\begin{figure}[h] + \centerline{\includegraphics[scale=.65]{fig/fsm}} + \caption{Main FSM of \textit{vbcp\_wb} module} + \label{fig:fsm} +\end{figure} + +\begin{table}[h] + \caption{States of \textit{vbcp\_wb} FSM} + \label{tbl:fsm} + \centerline + { + \begin{tabular}{l p{.7\textwidth}} + \hline + \multicolumn{1}{c}{\textbf{State}} & \multicolumn{1}{c}{\textbf{Description}} \\ + \hline + IDLE & Wait for the \textit{i2c\_slave} module to receive the VBCP + address and go to \textit{WB\_ADR}. The starting value at the + \textit{op\_o} output of the \textit{i2c\_slave} module is stored + for checking in \textit{OPER} \\ + WB\_ADR & Shift in the two address bytes sent via VBCP and go to + \textit{SIM\_WB\_TRANSF} \\ + SIM\_WB\_TRANSF & Start a Wishbone read transfer from address received in previous + state and go to \textit{OPER} if Wishbone address exists (Wishbone + \textit{ack} received), or \textit{IDLE} otherwise (Wishbone \textit{err} + received) \\ + OPER & Check the \textit{op\_o} output of the \textit{i2c\_slave} module. + If different from the value at the start, go to \textit{SYSMON\_RD\_WB} state + (SysMon is reading from \textit{vbcp\_wb}), otherwise continue shifting + in bytes (SysMon writing to \textit{vbcp\_wb}) \\ + SYSMON\_WR & Continue reading up to four bytes sent by the SysMon and go to + \textit{SYSMON\_WR\_WB}\\ + SYSMON\_WR\_WB & Perform a Wishbone write transfer to the register with the address obtained in + \textit{WB\_ADR} \\ + SYSMON\_RD\_WB & Perform a Wishbone read transfer from the address obtained in + \textit{WB\_ADR} and go to \textit{SYSMON\_RD} \\ + SYSMON\_RD & Shift out the four bytes of the Wishbone register when the \textit{i2c\_slave} + module successfully finishes a write \\ + \hline + \end{tabular} + } +\end{table} + +When the \textit{i2c\_slave} module finishes a transfer (signaled by a \textit{done\_p\_o} pulse), +the status is checked and if it is as expected (e.g., \textit{address good} while in the +\textit{IDLE} state), the FSM advances to the next state. Where the SysMon appears in the state +names, it indicates what the SysMon action is. For example, if the state of the FSM is +\textit{SYSMON\_WR}, this means the SysMon is writing and the \textit{vbcp\_wb} is reading. + +To better understand how the FSM operates, Figures \ref{fig:sysmon-wr-fsm} and +\ref{fig:sysmon-rd-fsm} can be consulted, where the state of the FSM is shown +during reads and writes from the SysMon. + +When the SysMon writes (Figure~\ref{fig:sysmon-wr-fsm}), the +\textit{vbcp\_wb} module waits in the \textit{IDLE} state until +the I$^2$C address is received, then, while in the \textit{WB\_ADR} state, +it shifts in the Wishbone address. A Wishbone transfer is then simulated with +the received the address and if this address exists (a Wishbone \textit{ack} +is received), the first byte is shifted in while in the \textit{OPER} state, +followed by the next three bytes while in the \textit{SYSMON\_WR} state. +Finally, the register is written to in the \textit{SYSMON\_WR\_WB} state. + +When the SysMon reads (Figure~\ref{fig:sysmon-rd-fsm}), the first few +steps are the same as for a read. The address is shifted in and +checked in the Wishbone transfer simulation state. In the case of a SysMon +reading from a board, however, the I$^2$C transfer is restarted and the order +is reversed (SysMon starts reading). Thus, while in \textit{OPER}, the FSM +detects a different value of \textit{op\_o} and goes into the +\textit{SYSMON\_RD\_WB} state. The value of the register is read while in this +state, and sent via VBCP in the \textit{SYSMON\_RD} state. + +\begin{figure}[h] + \centerline{\includegraphics[width=\textwidth]{fig/sysmon-wr-fsm}} + \caption{FSM states when the SysMon writes to the \textit{vbcp\_wb}} + \label{fig:sysmon-wr-fsm} +\end{figure} + +\begin{figure}[h] + \centerline{\includegraphics[width=\textwidth]{fig/sysmon-rd-fsm}} + \caption{FSM states when the SysMon reads from the \textit{vbcp\_wb}} + \label{fig:sysmon-rd-fsm} +\end{figure} + +%============================================================================== +% SEC: Synthesis results +%============================================================================== +\section{Synthesis results} +\label{sec:synth-res} + +The synthesis results for the \textit{vbcp\_wb} design using \textit{xst} +on the Spartan-6 XC6SLX45T are shown in Table~\ref{tbl:synth-res}. + +\begin{table}[h] + \caption{Synthesis results} + \label{tbl:synth-res} + \centerline{ + \begin{tabular}{l c c c} + \hline + \multicolumn{1}{c}{\textbf{Resource}} & \textbf{Used} & \textbf{Available} & \textbf{\%} \\ + \hline + Slices & 76 & 6822 & 1.1 \\ + Slice registers & 172 & 54576 & 0.3 \\ + LUTs & 151 & 27288 & 0.6 \\ + \hline + \end{tabular} + } +\end{table} + +%============================================================================== +% Bibliography +%============================================================================== +\pagebreak +\bibliographystyle{ieeetr} +\bibliography{wb_i2c_bridge} + +\end{document} diff --git a/doc/wb_xil_multiboot/Makefile b/doc/wb_xil_multiboot/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..97de2e73e2c1227abab81342cea019f54599a3a7 --- /dev/null +++ b/doc/wb_xil_multiboot/Makefile @@ -0,0 +1,14 @@ +FILE=wb_xil_multiboot + +all: + $(MAKE) -C fig + pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex + bibtex $(FILE).aux + pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex + pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex + evince $(FILE).pdf & + +clean: + $(MAKE) -C fig clean + rm -rf *.aux *.dvi *.log $(FILE).pdf *.lof *.lot *.out *.toc *.bbl *.blg *.gz + diff --git a/doc/wb_xil_multiboot/README.txt b/doc/wb_xil_multiboot/README.txt new file mode 100644 index 0000000000000000000000000000000000000000..e69d1177f1e40e729e63801d1f69fcf7653bf564 --- /dev/null +++ b/doc/wb_xil_multiboot/README.txt @@ -0,0 +1,4 @@ +Type 'make' to create your .pdf documentation file. + +You need Inkscape to make the documentation files: +sudo apt-get install inkscape \ No newline at end of file diff --git a/doc/wb_xil_multiboot/cern-title.tex b/doc/wb_xil_multiboot/cern-title.tex new file mode 100644 index 0000000000000000000000000000000000000000..f8aeeb1b697b1def6e193c1d2491e3eface795e4 --- /dev/null +++ b/doc/wb_xil_multiboot/cern-title.tex @@ -0,0 +1,31 @@ +\begin{titlepage} + +\vspace*{3cm} + +%--------------------------------------------------------------- +% name +%--------------------------------------------------------------- +\noindent{\LARGE \textbf{Xilinx MultiBoot module}} + +\noindent \rule{\textwidth}{.1cm} + +\hfill\today + +\vspace*{3cm} + +\begin{figure}[h] + \includegraphics[height=3cm]{fig/cern-logo} + \hfill + \includegraphics[height=3cm]{fig/ohwr-logo} +\end{figure} + +\vfill + +%--------------------------------------------------------------- +% name +%--------------------------------------------------------------- +\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}} + +\noindent \rule{\textwidth}{.05cm} + +\end{titlepage} diff --git a/doc/wb_xil_multiboot/fig/Makefile b/doc/wb_xil_multiboot/fig/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..00fe82ab1dec0a92d0f8fbd96f7690b50f105166 --- /dev/null +++ b/doc/wb_xil_multiboot/fig/Makefile @@ -0,0 +1,11 @@ +SRC = $(wildcard *.svg) +OBJS = $(SRC:.svg=.pdf) + +all: $(OBJS) + echo $(OBJS) + +%.pdf : %.svg + inkscape -f $< -A $@ + +clean : + rm -f *.pdf diff --git a/doc/wb_xil_multiboot/fig/cern-logo.svg b/doc/wb_xil_multiboot/fig/cern-logo.svg new file mode 100644 index 0000000000000000000000000000000000000000..470c7b0a157435f6443c68c4dd45248e68624585 --- /dev/null +++ b/doc/wb_xil_multiboot/fig/cern-logo.svg @@ -0,0 +1,53 @@ +<?xml version="1.0" encoding="utf-8"?> +<!-- Generator: Adobe Illustrator 15.0.2, SVG Export Plug-In . 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+@misc{ug380, + title = {{UG380 - Spartan-6 Configuration Guide}}, + author = {Xilinx}, + month = jan, + year = {2013}, + note = {v2.5}, + howpublished = {\url{http://www.xilinx.com/support/documentation/user_guides/ug380.pdf}} +} + +@misc{xtp059, + title = {{XTP059: SP605 MultiBoot Design}}, + howpublished = {\url{http://www.xilinx.com/support/documentation/boards_and_kits/xtp059.pdf}}, + urldate = {2013-10-25}, + publisher = {Dec. 2009}, + author = {Xilinx}, + file = {XTP059: SP605 MultiBoot Design} +} + +@misc{xil-multiboot-ohwr, + title = {{Xilinx MultiBoot module Project Page on OHWR}}, + howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo-gw/wiki/Xil_multiboot}}, + urldate = {2013-10-25}, + author = {Stana, Theodor-Adrian}, + month = oct, + year = {2013} +} + +@misc{gen-bitstream, + title = {{Generating Bitstreams for MultiBoot designs (Xilinx MultiBoot module Project Page on OHWR)}}, + howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo-gw/wiki/Xil_multiboot#Generating-bitstreams-for-Xilinx-FPGA-reprogramming}}, + urldate = {2013-10-25}, + author = {Stana, Theodor-Adrian}, + month = oct, + year = {2013} +} + +@misc{gencores-ohwr, + title = {{Generic Cores Library OHWR Project Page}}, + howpublished = {\url{http://www.ohwr.org/projects/general-cores/wiki}} +} + +@misc{ctb-proj, + title = {{CONV-TTL-BLO Project Page on OHWR}}, + howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo/wiki}}, + month = oct, + year = {2013} +} + +@misc{ctb-repo, + title = {{CONV-TTL-BLO Gateware Repository on OHWR}}, + howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo-gw/repository}}, + month = oct, + year = {2013} +} + +@misc{xil-devref, + title = {{Xilinx Command Line Tools User Guide (UG628)}}, + howpublished = {\url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/devref.pdf}}, + author = {Xilinx}, + month = jul, + year = {2012} +} diff --git a/doc/wb_xil_multiboot/wb_xil_multiboot.tex b/doc/wb_xil_multiboot/wb_xil_multiboot.tex new file mode 100644 index 0000000000000000000000000000000000000000..6dddb4c0133a608adfa33c293d520b61f93a5901 --- /dev/null +++ b/doc/wb_xil_multiboot/wb_xil_multiboot.tex @@ -0,0 +1,947 @@ +%============================================================================== +% Document Header +%============================================================================== +\documentclass[a4paper,11pt]{article} + +% Color package +\usepackage[usenames,dvipsnames]{color} + +% Hyperrefs +\usepackage[ + colorlinks = true, + linkcolor = Mahogany, + citecolor = Mahogany, + urlcolor = blue, +]{hyperref} + +\usepackage{graphicx} +\usepackage{multirow} + +\usepackage{color} + +\usepackage[toc,page]{appendix} + +\usepackage{listings} + +% Header and footer customization +\usepackage{fancyhdr} +\setlength{\headheight}{15.2pt} +\pagestyle{fancy} +\fancyhead[L]{\nouppercase{\leftmark}} +\fancyhead[R]{} +\renewcommand{\footrulewidth}{0.4pt} + +% Row number command +\newcounter{rownr} +\newcommand{\rownumber}{\stepcounter{rownr}\arabic{rownr}} + +%============================================================================== +% Start of document +%============================================================================== +\begin{document} + +%------------------------------------------------------------------------------ +% Title +%------------------------------------------------------------------------------ +\include{cern-title} + +%------------------------------------------------------------------------------ +% Revision history +%------------------------------------------------------------------------------ +\thispagestyle{empty} +\section*{Revision history} + +\centerline +{ + \begin{tabular}{l c p{.6\textwidth}} + \hline + \multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\ + \hline + 28-10-2013 & 0.1 & First draft \\ + \hline + \end{tabular} +} + +\pagebreak +\pagenumbering{roman} +\setcounter{page}{1} +\tableofcontents + +%------------------------------------------------------------------------------ +% List of figs, tables, abbrevs +%------------------------------------------------------------------------------ +\pagebreak +\listoffigures +\listoftables + +\section*{List of Abbreviations} +\begin{tabular}{l l} +FPGA & Field-Programmable Gate Array \\ +IPROG & Internal PROGRAM\_B \\ +OHWR & Open Hardware Repository \\ +PROM & Programmable Read-Only Memory \\ +SPI & Serial Peripheral Interface \\ +\end{tabular} + +\pagebreak +\pagenumbering{arabic} +\setcounter{page}{1} + +%============================================================================== +% SEC: Intro +%============================================================================== +\section{Introduction} +\label{sec:intro} + +Xilinx MultiBoot technology~\cite{ug380} allows reprogramming an FPGA by downloading a +bitstream to a PROM chip external to the FPGA and then issuing an IPROG (Internal +PROGRAM\_B) command to the configuration logic of the FPGA. This command triggers +deletion of the FPGA configuration and rewriting it with the new configuration +written to the PROM. + +This document describes \textit{xil\_multiboot}, an Open Hardware (OHWR) \cite{ohwr} +FPGA design that can be used to remotely reprogram a Xilinx Spartan-6 FPGA using +MultiBoot technology. + +\begin{figure}[h] + \centerline{\includegraphics[width=\textwidth]{fig/multiboot-bd}} + \label{fig:multiboot-bd} + \caption{Block diagram of \textit{xil\_multiboot} module} +\end{figure} + +The main features of the \textit{xil\_multiboot} module are: +\begin{itemize} + \item software controls operation of the module + \begin{itemize} + \item Wishbone interface implements registers for control and status readout + \item writing FPGA bitstream data to the flash chip + \item issuing reprogramming command to the FPGA (via Xilinx ICAP) + \item reading boot status register from the FPGA configuration logic (via Xilinx ICAP) + \end{itemize} + \item a finite-state machine (FSM) controls writing to the flash chip and sending the + reprogramming command to the FPGA + \item modular, easily modifiable design + \begin{itemize} + \item PROM chip is controlled by software, so virtually any 8-bit SPI PROM chip is + supported by writing software to send the various commands to the chip + \item Wishbone interface can easily be replaced by some other interconnect (e.g., AXI) + \end{itemize} +\end{itemize} + +A block diagram of the \textit{xil\_multiboot} module is shown in Figure~\ref{fig:multiboot-bd}. +Users can write bitstream data to a flash by writing each byte of the bitstream to a module register +(in the \textit{multiboot\_regs}) module. Writing to the flash is done via the \textit{spi\_master} +module under the control of the finite-state machine (FSM) module (\textit{multiboot\_fsm}). After the +bitstream has been written to the flash module, a remote reprogramming command is sent +to the configuration logic by setting a bit in one of the control registers. The +Xilinx \textit{ICAP\_SPARTAN6} primitive is the interface between the \textit{xil\_multiboot} +module and the FPGA configuration logic. + +For the rest of the document, the external PROM chip that the FPGA uses to +program itself will be referred to as flash, since a flash chip was used +as the external PROM during the design of the module. However, this does not +mean \textit{xil\_multiboot} works only with flash chips. Any 8-bit SPI PROM +should be usable with the \textit{xil\_multiboot} design. + +%============================================================================== +% SEC: Instantiation +%============================================================================== +\section{Instantiation} +\label{sec:instantiation} + +Table~\ref{tbl:ports} lists the ports of the \textit{xil\_multiboot} module. +In order to instantiate the MultiBoot module, one needs to connect +the Wishbone slave ports to a Wishbone master, such as the \textit{xwb\_crossbar} +Wishbone crossbar module on OHWR \cite{gencores-ohwr}. The SPI ports should be +connected directly to the FPGA output ports connected to the flash chip. + +\begin{table}[h] + \caption{Ports of the Xilinx MultiBoot module} + \label{tbl:ports} + \centerline + { + \begin{tabular}{l c p{.6\textwidth}} + \hline + \multicolumn{1}{c}{\textbf{Port}} & \textbf{Size} & \multicolumn{1}{c}{\textbf{Description}} \\ + \hline + clk\_i & 1 & Clock input \\ + rst\_n\_i & 1 & Active-low reset input \\ + wbs\_i & & Wishbone slave interface inputs \\ + wbs\_o & & Wishbone slave interface outputs \\ + spi\_cs\_n\_o & 1 & Active-low chip select output \\ + spi\_sclk\_o & 1 & SPI clock output \\ + spi\_mosi\_o & 1 & SPI data output line (Master Out, Serial In) \\ + spi\_miso\_i & 1 & SPI data input line (Master In, Serial Out) \\ + \hline + \end{tabular} + } +\end{table} + +Note that in order to use the module, the OHWR \textit{general-cores} +library~\cite{gencores-ohwr} needs to be imported into the design. This library is where +the structures for the Wishbone slave interface ports (\textit{wbs\_i} and \textit{wbs\_o}) +are defined. + +%============================================================================== +% SEC: Using +%============================================================================== +\pagebreak +\section{Using the Xilinx MultiBoot module} +\label{sec:instantiation} + +For an example project of where the Xilinx MultiBoot module is used, see the +CONV-TTL-BLO project~\cite{ctb-proj}. The firmware of this project, starting from +version 2.0, instantiates the MultiBoot module. The project also contains example +Python scripts for writing a bitstream to the flash. Refer to the project +webpage~\cite{ctb-proj} for more information. + +Table~\ref{tbl:workflow} shows the MultiBoot workflow~\cite{xtp059}. See \cite{gen-bitstream} +for pointers on how to generate a MultiBoot bitstream. The address map of the MultiBoot module +can be found in Appendix~\ref{app:memmap}. This appendix details the various registers the +user should write as part of the MultiBoot workflow. + +\setcounter{rownr}{0} + +\begin{table}[h] + \caption{MultiBoot workflow} + \label{tbl:workflow} + \centerline { + \begin{tabular}{c p{.7\textwidth}} + \hline + \textbf{Step} & \multicolumn{1}{c}{\textbf{Action}} \\ + \hline + \rownumber & Prepare a Xilinx FPGA bitstream \\ + \rownumber & Send the bitstream to the flash by writing to the FAR register \\ + \rownumber & Write the MultiBoot bitstream start address and flash chip read command + op-code into the MBBAR register \\ + \rownumber & Write the Golden bitstream start address and flash chip read command + op-code into the GBBAR register \\ + \rownumber & Unlock the IPROG bit in the FPGA by setting CR.IPROG\_UNL \\ + \rownumber & Issue a reprogramming command to the FPGA by setting CR.IPROG \\ + \hline + \end{tabular} + } +\end{table} + + +%============================================================================== +% SEC: MultiBoot +%============================================================================== +\section{Xilinx MultiBoot technology} +\label{sec:multiboot} + +Spartan-6 configuration logic is organized in a set of frames, which can be written to +or read from using 16-bit word transfers. A Spartan-6 FPGA bitstream consists of +commands that access the FPGA configuration logic to read and write these frames, +as well as the data for the configuration logic frames. + +When using the MultiBoot technology, multiple bitstreams exist for one FPGA. +These bitstreams are all stored on the attached flash chip and the user can +send a special instruction called IPROG (Internal PROGRAM\_B) to reprogram the +FPGA chip using one of the bitstreams on the flash. + +Most MultiBoot designs will contain at least three bitstreams, as shown in +Figure~\ref{fig:multiboot}. When the FPGA board is powered on, if it is configured +in master mode configuration~\cite{ug380}, the FPGA will start loading a bitstream +from address zero of the attached flash chip. This is where the Header bitstream +resides. This small bitstream contains a synchronization word for the configuration +logic, sets the start address of the MultiBoot and Golden bitstreams and sends +an IPROG command to the configuration logic. + +\begin{figure} + \centerline{\includegraphics[scale=.45]{fig/multiboot}} + \label{fig:multiboot} + \caption{Bitstreams in a MultiBoot design} +\end{figure} + +The IPROG command causes the configuration logic to start loading the MultiBoot +bitstream from the flash chip, starting at the given MultiBoot address. If the MultiBoot +bitstream fails to load three times (see below for bitstream load failure reasons), +the configuration logic falls back to the Golden bitstream. This is a bitstream +which is known to be safe, should the MultiBoot bitstream be corrupted on load. + +Should the Golden bitstream also be corrupted, the configuration logic +tries to load it three times and then returns to the Header bitstream. When here, +the configuration logic attempts to load the MultiBoot and Golden bitstreams three +more times, before configuration failure. + +A strike counter is used to select between which of the three bitstreams is loaded. +This strike counter is stored in the configuration BOOTSTS register and can only be +reset by a power-on reset or by pulsing the FPGA's PROGRAM\_B pin. The strike counter +is shared among the three bitsreams; as Figure~\ref{fig:multiboot} shows and as just +described, each bitstream is selected based on the value of this counter: + +\begin{itemize} + \item if it is 0..2, the MultiBoot bitstream gets loaded + \item if it is 3..5, the Golden bitstream gets loaded + \item if it is 6..8, the Header bitstream gets loaded, and MultiBoot and Golden + bitstreams are attempted three more times + \item if it is 9, configuration is halted +\end{itemize} + +%------------------------------------------------------------------------------ +\subsection{Reasons for bitstream load failure} + +There are two ways in which a bitstream load can fail: +\begin{itemize} + \item synchronization word Watchdog timeout + \item bitstream CRC error +\end{itemize} + +Prior to performing any work, the FPGA configuration logic looks for a synchronization word +in the bitstream. This synchronization word is shown in Table~\ref{tbl:sync-word}. The +configuration logic contains a Watchdog timer that counts down from a value specified by +the Xilinx \textit{bitgen} tool when the bitstream is generated (see Table~\ref{tbl:bitgen}). +The Watchdog is disabled when the synchronization word is found. If the Watchdog timer +times out, the strike count is incremented and configuration is reattempted as described above. + +Note that the Watchdog timer is only enabled in master configuration modes, when +configuration restarts. It is disabled when the synchronization word is found, +or when the FPGA uses one of the other configuration modes~\cite{ug380}. + +\begin{table}[h] + \label{tbl:sync-word} + \caption{Bitstream synchronization word} + \centerline { + \begin{tabular}{c c c c} + \hline + \textbf{31 .. 24} & \textbf{23..16} & \textbf{15..8} & \textbf{7..0} \\ + \hline + 0xAA & 0x99 & 0x55 & 0x66 \\ + \hline + \end{tabular} + } +\end{table} + +The second failure mode of the configuration is based on the bitstream CRC. Each +bitstream contains at the end a CRC word which the configuration logic checks +before putting the FPGA in running mode. If the CRC at the end of the bitstream +does not correspond to what the configuration logic computes, a CRC error occurs +and the strike count is incremented as described above. + +\begin{table}[h] + \label{tbl:bitgen} + \caption{\textit{bitgen} flags} + \centerline { + \begin{tabular}{l l p{.6\textwidth}} + \hline + \multicolumn{1}{c}{\textbf{Flag}} & \multicolumn{1}{c}{\textbf{Setting}} & \multicolumn{1}{c}{\textbf{Description}} \\ + \hline + -g reset\_on\_err & Yes & Enables the strike count mechanism for retrying to load + the bitstream \\ + -g CRC & Enable & Enables the generation of a CRC at the end of the bitstream \\ + -g TIMER\_CFG & 1fff & Sets the watchdog timeout value to 8191 CCLK cycles \\ + \hline + \end{tabular} + } +\end{table} + +For configuration to be reattempted and to be able to generate configuration +errors, the configuration logic needs some information present in the bitstream. +This information can be provided by setting some \textit{bitgen} flags when +generating the bitstream. The necessary flags with the recommended settings +are listed in Table~\ref{tbl:bitgen}. For more information on \textit{bitgen} +and these flags, refer to \cite{xil-devref}. + +%------------------------------------------------------------------------------ +\subsection{Generating the bitstreams} + +Refer to \cite{gen-bitstream} for information on how to generate the various +bitstreams for a MultiBoot design. + +%------------------------------------------------------------------------------ +\subsection{Important note regarding MultiBoot bitstreams} + +Users should be aware that they should include the \textit{xil\_multiboot} module +when generating a new MultiBoot bitsream. Otherwise, once a bitstream without +the \textit{xil\_multiboot} module inside it is loaded into the FPGA, the +remote reprogramming capability of the FPGA is lost, and the user will need +to use JTAG or other means to program the FPGA with a MultiBoot-enabled design. + +Thus, always remember to include the \textit{xil\_multiboot} module in any bitstream +generated after the Golden bitstream. + +%============================================================================== +% SEC: Implementation +%============================================================================== +\section{Implementation} +\label{sec:implem} + +A block diagram of the design has already been presented in +Figure~\ref{fig:multiboot-bd}. This section describes the actions of the sub-modules +in the \textit{xil\_multiboot} module. The description is rather high-level, +some details are omitted for ease of understanding. The main purpose of this +section is for the reader to understand how the MultiBoot module works together with +the flash chip and the configuration logic to achieve FPGA reprogramming, rather +than specifying every detail about the module and its sub-modules. + +For more involved details, the user is free to consult the code in the project +repository~\cite{ctb-repo}. + +The \textit{multiboot\_fsm} module is at the heart of the design. It implements +a finite-state machine (FSM) with 34 states, which controls operation of the module. +A simplified diagram of the FSM is shown in Figure~\ref{fig:fsm}. The diagram shows the various +phases the FSM is in, and Table~\ref{tbl:fsm} lists these phases. Bear in mind +that each phase may contain multiple FSM states. However, many of these states +are just steps of accessing configuration logic through the Xilinx ICAP module, +so for simplicity they are not listed in this manual. Refer to the code for +more complete description. + +\begin{figure}[h] + \centerline{\includegraphics[width=.9\textwidth]{fig/fsm}} + \caption{Phases of the \textit{multiboot\_fsm}} + \label{fig:fsm} +\end{figure} + +\begin{table}[h] + \caption{Phases of the \textit{multiboot\_fsm}} + \label{tbl:fsm} + \centerline { + \begin{tabular}{p{.185\textwidth} p{.7\textwidth}} + \hline + \multicolumn{1}{c}{\textbf{Phase}} & \multicolumn{1}{c}{\textbf{Description}} \\ + \hline + \textbf{IDLE} & Wait for one of the following control bits to be set: \newline + CR.RDCFGREG \newline + CR.IPROG \newline + FAR.XFER \\ + \textbf{SPI transfer} & Shift out NBYTES of the three DATA fields in the FAR register, + and simultaneously shift in data received from the flash \newline + When NBYTES have been sent, FAR.READY is written high and + the FSM returns to IDLE \\ + \textbf{IPROG} & IPROG sequence (Table 7-1, p.130~\cite{ug380}) \\ + \textbf{Read status register} & Configuration register readout sequence (Table 6-1, p.113~\cite{ug380}) \\ + \hline + \end{tabular} + } +\end{table} + +%------------------------------------------------------------------------------ +\subsection{Sending data to the flash chip} +\label{sec:implem-spi} + +Table~\ref{tbl:data-seq} summarizes the flash read and write sequence. A more verbose +description is offered below. + +\setcounter{rownr}{0} + +\begin{table}[h] + \caption{Flash data sequence} + \label{tbl:data-seq} + \centerline{ + \begin{tabular}{c p{.7\textwidth}} + \hline + \textbf{Step} & \multicolumn{1}{c}{\textbf{Action}} \\ + \hline + \rownumber & User sets FAR.NBYTES to the number of data bytes to write \\ + \rownumber & User writes NBYTES FAR.DATA fields with the data to send to the flash \\ + \rownumber & User sets FAR.CS to '1' for a transfer with the flash chip enabled, or + to '0' for a dummy transfer (e.g., wait interval between flash commands, + with the chip select high) \\ + \rownumber & User sets FAR.XFER to '1' to start the SPI transfer \newline + (FAR.XFER is automatically cleared by hardware) \\ + \rownumber & The \textit{multiboot\_fsm} starts shifting out NBYTES DATA fields + to the \textit{spi\_master}, starting with DATA[0] \\ + \rownumber & The \textit{spi\_master} handles shifting out each bit in a byte \\ + \rownumber & When done, the \textit{spi\_master} signals the \textit{multiboot\_fsm}, + which shifts out the next byte (if NBYTES $>$ 0) \\ + \rownumber & When NBYTES bytes have been shifted out, the \textit{multiboot\_fsm} + sets the FAR.READY bit \\ + \rownumber & After FAR.READY is set, NBYTES DATA fields contain data retrieved from + the flash \\ + \hline + \end{tabular} + } +\end{table} + +Data to be sent to the flash chip is written in the FAR (see Appendix~\ref{app:far}). +Up to three data bytes can be sent via the FAR during one transfer phase. These data +bytes are written in the DATA fields in little-endian order. The NBYTES field selects +how many of the DATA fields contain bytes to send. Setting XFER to '1' with CS set to +'1' starts the transfer. Setting XFER to '1' with CS set to '0' starts a dummy +transfer, with the flash chip not selected. + +The transfer is performed via the \textit{spi\_master} module, which handles the +shifting of each DATA byte to the flash. However, the \textit{spi\_master} module +can only send one byte at a time, so the \textit{multiboot\_fsm} module handles +shifting bytes to the \textit{spi\_master}. After a byte has been transferred +between the FPGA and the flash, the \textit{multiboot\_fsm} places the byte +returned from the flash into the DATA byte that has just been sent. For example, +after sending DATA[0], the byte received from the flash is placed into DATA[0]; +after sending DATA[1], the byte received from the flash is placed into DATA[1]. + +When NBYTES data transfers have been completed, the \textit{multiboot\_fsm} sets +the signal for the FAR.READY bit to '1', to signal a completed transfer. The user +can now read the DATA fields for data retrieved from the flash. + +The feature of using more than one DATA field in the FAR is useful when a lower-speed +interface than SPI is used to access the FAR register (e.g., the VBCP interface in +the CONV-TTL-BLO project~\cite{ctb-proj}). If the interface used to access the FAR +is fast, only one byte in the FAR register may be used, and NBYTES left to 0. + +Appendix~\ref{app:multiple-spi} gives an example of how data can be written to flash. + +The following settings are used for the SPI communication (Figure~\ref{fig:spi-mode}). +\begin{itemize} + \item CPOL = 0 + \item CPHA = 0 +\end{itemize} + +\begin{figure}[h] + \centerline{\includegraphics[width=.7\textwidth]{fig/spi-mode}} + \caption{SPI settings (source: Wikipedia)} + \label{fig:spi-mode} +\end{figure} + +This yields that data bits are shifted out from the FPGA on the falling edge of SCLK +and shifted in from the flash chip on the rising edge of SCLK. + +%------------------------------------------------------------------------------ +\subsection{Reading FPGA configuration registers} +\label{sec:implem-rdcfgreg} + +The Spartan-6 FPGA contains registers which can be read to get the stauts of the +configuration logic. In order to read these registers, a special sequence must be +followed. The sequece (listed in Table 6-1 of~\cite{ug380}) is implemented in the +\textit{multiboot\_fsm}. Table~\ref{tbl:rdcfgreg-seq} lists the sequence users +should follow to read out an FPGA configuration register via the \textit{xil\_multiboot} +module. + +\setcounter{rownr}{0} + +\begin{table}[h] + \caption{Configuration register readout via \textit{xil\_multiboot}} + \label{tbl:rdcfgreg-seq} + \centerline { + \begin{tabular}{c p{.7\textwidth}} + \hline + \multicolumn{1}{c}{\textbf{Step}} & \multicolumn{1}{c}{\textbf{Action}} \\ + \hline + \rownumber & User writes the FPGA configuration register address (Table 5-30, p.94~\cite{ug380}) + in the CFGREGADR field of the CR \\ + \rownumber & User sets the CR.RDCFGREG bit to '1' to initiate a configuration register + read via the ICAP module \newline + (CR.RDCFGREG is automatically cleared by hardware) \\ + \rownumber & The \textit{multiboot\_fsm} performs the sequence in Table 6-1, p.113~\cite{ug380} + and returns one 16-bit value of the configuration register to the CFGREGIMG + field of IMGR and sets the VALID bit of the same register to '1' \\ + \rownumber & The user reads the configuration register value from IMGR.CFGREGIMG if the + VALID bit is '1' \\ + \hline + \end{tabular} + } +\end{table} + +When the user sets the RDCFGREG bit in the \textit{xil\_multiboot} control register (CR), +the \textit{multiboot\_fsm} initiates the configuration register readout sequence. +It first sends a synchronization word, and then takes the value of CFGREGADR from +the CR and use it to build a Type 1 configuration frame to read the configuration +register (see~\cite{ug380}, p.~93 for more details). The configuration logic will +respond to this frame with the value of the configuration register. This value is +placed in the CFGREGIMG field of the image register, and the \textit{multiboot\_fsm} +continues to perform the final steps of the configuration register readout sequence, +prior to returning to IDLE. + +Note that some configuration registers in the Spartan-6 FPGA are more than 16 bits wide. +The \textit{xil\_multiboot} module does not support reading the full length of the +registers; it can only return the least significant 16 bits of the registers. + +%------------------------------------------------------------------------------ +\subsection{Sending the IPROG command} + +Table~\ref{tbl:iprog} lists the actions needed to issue the IPROG command to the +FPGA using the \textit{xil\_multiboot} module. When the IPROG bit is set in the CR, +the \textit{multiboot\_fsm} handles sending the IPROG sequence (Table 7-1, +p.130~\cite{ug380}) to the ICAP. + +\setcounter{rownr}{0} + +\begin{table}[h] + \caption{Sequence for sending the IPROG command} + \label{tbl:iprog} + \centerline { + \begin{tabular}{c p{.7\textwidth}} + \hline + \textbf{Step} & \multicolumn{1}{c}{\textbf{Action}} \\ + \hline + \rownumber & User sends the bitstream to the flash chip (Section~\ref{sec:implem-spi}) \\ + \rownumber & User sets the IPROG\_UNL bit in the CR \\ + \rownumber & User sets the IPROG bit in the CR \\ + \rownumber & The \textit{multiboot\_fsm} performs the sequence in Table 7-1, p.130~\cite{ug380} + and sends the IPROG command \\ + \rownumber & The FPGA starts deleting the configuration logic and loading the + new bitstream from the flash \\ + \rownumber & After configuration finishes, the user reads the custom firmware + version number register to see that the reprogramming was successful \\ + \hline + \end{tabular} + } +\end{table} + +Note that after the IPROG command is sent, the FPGA starts the reconfiguration +sequence and communication to it will be lost until the new bitstream is loaded +is sent. + +The user should implement some form of firmware version numbering to detect whether +an IPROG succeeds. This version number can be stored into a read-only register in the +FPGA and read after the IPROG command. An example of this is given in the CONV-TTL-BLO +project~\cite{ctb-proj}. + +%============================================================================== +% SEC: Modifying +%============================================================================== +\section{Modifying the design} +\label{sec:modify} + +The \textit{xil\_multiboot} module is purposely modular in case users want to +interface to different FPGA interconnect standards, or different flash chips. +In order to make modifications to the design, knowledge of VHDL is required. + +If the user would like to adapt the design for a new FPGA interconnect standard, +the steps to be followed are listed in Table~\ref{tbl:ch-intercon}. + +\setcounter{rownr}{0} + +\begin{table}[h] + \caption{Changing the Wishbone interconnect} + \label{tbl:ch-intercon} + \centerline { + \begin{tabular}{c p{.7\textwidth}} + \hline + \textbf{Step} & \multicolumn{1}{c}{\textbf{Action}} \\ + \hline + \rownumber & Change \textit{wbs\_i} and \textit{wbs\_o} in \textit{xil\_multiboot} + ports to the preferred interconnect ports \\ + \rownumber & Implement or change the current \textit{multiboot\_regs} + module, keeping the interface to the FSM side (e.g., the + \textit{multiboot\_cr\_iprog\_o} port, etc.) \\ + \rownumber & Instantiate the new \textit{multiboot\_regs} module into the + \textit{xil\_multiboot} module \\ + \hline + \end{tabular} + } +\end{table} + +The SPI interface to the flash chip is hardwired to the settings listed in +Section~\ref{sec:implem-spi}. Table~\ref{tbl:ch-spi} lists the steps to be +performed in case these SPI settings need to be changed. + +\setcounter{rownr}{0} + +\begin{table}[h] + \caption{Modifying SPI settings} + \label{tbl:ch-spi} + \centerline { + \begin{tabular}{c p{.7\textwidth}} + \hline + \textbf{Step} & \multicolumn{1}{c}{\textbf{Action}} \\ + \hline + \rownumber & First, see if the CPOL setting alone will not fix the problem. + If so, simply change the \textit{cpol\_i} port value where + the \textit{spi\_master} is instantiated \\ + \rownumber & Change the design of the \textit{spi\_master} module; it is an + easy-to-follow FSM design \\ + \hline + \end{tabular} + } +\end{table} + +Another potential addition to the design would be the capability of reading +the full value of all FPGA configuration registers. As outlined in +Section~\ref{sec:implem-rdcfgreg}, some configuration registers are more than +16 bits in length, and the \textit{xil\_multiboot} module cannot return their full +value. This can be modified by, implementing an extra COUNT field in the CR; +the \textit{multiboot\_fsm} can then use this field to build a Type 1 configuration +package to return the full length of the configuration register. More information +on this can be found in the Configuration Packets section of~\cite{ug380}. + +%============================================================================== +% SEC: Synthesis results +%============================================================================== +\section{Synthesis results} +\label{sec:synth-res} + +The synthesis results for the \textit{xil\_multiboot} design using \textit{xst} +on the Spartan-6 XC6SLX45T are shown in Table~\ref{tbl:synth-res}. + +\begin{table}[h] + \caption{Synthesis results} + \label{tbl:synth-res} + \centerline{ + \begin{tabular}{l c c c} + \hline + \multicolumn{1}{c}{\textbf{Resource}} & \textbf{Used} & \textbf{Available} & \textbf{\%} \\ + \hline + Slices & 123 & 6822 & 1.8 \\ + Slice registers & 270 & 54576 & 0.5 \\ + LUTs & 332 & 27288 & 1.2 \\ + \hline + \end{tabular} + } +\end{table} + +%============================================================================== +% Appendices +%============================================================================== +\pagebreak +\begin{appendices} +%------------------------------------------------------------------------------ +% APP: Memmap +%------------------------------------------------------------------------------ +\section{Memory map} +\label{app:memmap} + +The memory map of the Xilinx MultiBoot module is shown below. The following +sections detail the fields of each register. + +\vspace*{11pt} + +\centerline +{ + \begin{tabular}{l l p{.6\textwidth}} + \textbf{Offset} & \textbf{Name} & \textbf{Description} \\ + 0x00 & CR & Control Register \\ + 0x04 & SR & Status register \\ + 0x08 & GBBAR & Golden Bitstream Base Address Register \\ + 0x0c & MBBAR & Multiboot Bitstream Base Address Register \\ + 0x10 & FAR & Flash access register \\ + \end{tabular} +} + +%------------------------------------------------------------------------------ +\subsection{CR -- Control Register} +\label{app:cr} + +\begin{tabular}{l l c c l} +\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\ +31..18 & \textit{Reserved} & -- & X & \\ +17 & IPROG & R/W & 0 & IPROG bit \\ +16 & IPROG\_UNL & R/W & 0 & IPROG unlock bit \\ +15..7 & \textit{Reserved} & -- & X & \\ +6 & RDCFGREG & R/W & 0 & Read config register \\ +5..0 & CFGREGADR & R/W & 0 & Config register address \\ +\end{tabular} + +\vspace*{11pt} + +\noindent +{ + \begin{tabular}{l p{.7\textwidth}} + \textbf{Field} & \textbf{Description} \\ + \textit{Reserved} & Write as '0'; read undefined \\ + IPROG & When 1, it triggers the FSM to send the IPROG command to the ICAP controller \newline + This bit needs to be unlocked by setting the IPROG\_UNL bit in a previous cycle \\ + IPROG\_UNL & Unlock bit for the IPROG command. This bit needs to be set to 1 prior to writing + the IPROG bit \\ + RDCFGREG & Initiate a read from the FPGA configuration register at address CFGREGADR \newline + This bit is automatically cleared by hardware \\ + CFGREGADR & The address of the FPGA configuration register to read (see Configuration Registers + section in~\cite{ug380})\\ + \end{tabular} +} + +%------------------------------------------------------------------------------ +\subsection{IMGR -- Image Register} +\label{app:imgr} + +\begin{tabular}{l l c c l} +\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\ +31..17 & \textit{Reserved} & -- & X & \\ +16 & VALID & R/O & 0 & Image register is valid \\ +15..0 & CFGREGIMG & R/O & 0 & Config. register image \\ +\end{tabular} + +\vspace*{11pt} + +\noindent +{ + \begin{tabular}{l p{.7\textwidth}} + + \textbf{Field} & \textbf{Description} \\ + \textit{Reserved} & Write as '0'; read undefined \\ + VALID & A read has been performed from the FPGA configuration + register at address CR.CFGREGADR, and its value is + present in CFGREGIMG \\ + CFGREGIMG & Contains the value of the FPGA configuration register; + validated by the VALID bit (see Configuration Registers + section in~\cite{ug380}) \\ + \end{tabular} +} + +%------------------------------------------------------------------------------ +\subsection{GBBAR -- Golden Bitstream Base Address Register} +\label{app:gbbar} + +\begin{tabular}{l l c c l} +\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\ +31..24 & OPCODE & R/W & 0 & Flash chip read op-code \\ +23..0 & GBA & R/W & 0 & Golden Bitstream Address \\ +\end{tabular} + +\vspace*{11pt} + +\noindent +{ + \begin{tabular}{l p{.7\textwidth}} + + \textbf{Field} & \textbf{Description} \\ + OPCODE & Op-code for the flash chip read (or fast-read) command. Get + this value from the flash chip datasheet \\ + GBA & Start address of the Golden bitstream on the flash chip \\ + \end{tabular} +} + +\vspace*{11pt} + +%Guidelines on selecting a GBBAR: +% +%\begin{itemize} +% \item When generating the Header image via Xilinx ISE, the GBA is (normally) +% automatically set by the software to 0x44 +% \item If different than the default, the starting address of the Golden +% bitstream should be set to a flash sector boundary +%\end{itemize} + +%------------------------------------------------------------------------------ +\subsection{MBBAR -- MultiBoot Bitstream Base Address Register} +\label{app:mbbar} + +\begin{tabular}{l l c c l} +\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\ +31..24 & OPCODE & R/W & 0 & Flash chip read op-code \\ +23..0 & MBA & R/W & 0 & MultiBoot Bitstream Address \\ +\end{tabular} + +\vspace*{11pt} + +\noindent +{ + \begin{tabular}{l p{.7\textwidth}} + + \textbf{Field} & \textbf{Description} \\ + OPCODE & Op-code for the flash chip read (or fast-read) command. Get + this value from the flash chip datasheet \\ + MBA & Start address of the MultiBoot bitstream on the flash chip \\ + \end{tabular} +} + +\vspace*{11pt} + +%Guidelines on selecting an MBBAR: +% +%\begin{itemize} +% \item The MultiBoot bitstream should start on a flash sector boundary. +%\end{itemize} + +%------------------------------------------------------------------------------ +\subsection{FAR -- Flash Access Register} +\label{app:far} + +\begin{tabular}{l l c c l} +\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\ +31..29 & \textit{Reserved} & -- & 0 & Flash chip read op-code \\ +28 & READY & R & 1 & SPI access status \\ +27 & CS & R/W & 0 & SPI chip select \\ +26 & XFER & R/W & 0 & Start SPI transfer \\ +25..24 & NBYTES & R/W & 0 & Number of bytes to send \\ +23..16 & DATA[2] & R/W & 0 & Data at offset 2 \\ +15..8 & DATA[1] & R/W & 0 & Data at offset 1 \\ +7..0 & DATA[0] & R/W & 0 & Data at offset 0 \\ +\end{tabular} + +\vspace*{11pt} + +\noindent +{ + \begin{tabular}{l p{.7\textwidth}} + + \textbf{Field} & \textbf{Description} \\ + \textit{Reserved} & Write as '0'; read undefined \\ + READY & SPI transfer ready; NBYTES have been sent to the flash chip, + and NBYTES read from the chip present in DATA fields \\ + CS & SPI chip select. Note that this pin has opposite polarity + than the normal SPI chip select pin: \newline + '1' -- flash chip is selected (CS pin = 0) \newline + '0' -- flash chip is not selected (CS pin = 1) \\ + XFER & '1' -- starts SPI transfer \newline + This bit is automatically cleared by hardware \\ + NBYTES & Number of DATA fields to send in one transfer \newline + 0 -- send 1 byte (DATA[0]) \newline + 1 -- send 2 bytes (DATA[0], DATA[1]) \newline + 2 -- send 3 bytes (DATA[0], DATA[1], DATA[2]) \newline + 3 -- \textit{Reserved} \\ + DATA[2] & Write this register with the value of data byte 2 \newline + After an SPI transfer, this register contains the value of + data byte 2 read from the flash \\ + DATA[1] & Write this register with the value of data byte 1 \newline + After an SPI transfer, this register contains the value of + data byte 1 read from the flash \\ + DATA[0] & Write this register with the value of data byte 0 \newline + After an SPI transfer, this register contains the value of + data byte 0 read from the flash \\ + \end{tabular} +} + + +%============================================================================== +% APP: Multiple data fields +%============================================================================== +\pagebreak +\section{Sending multiple data fields in one SPI transfer} +\label{app:multiple-spi} + +The FAR register contains three bytes for data fields to be sent to the SPI +chip. As mentioned in Section~\ref{sec:implem-spi}, this can be used to send +data faster when the interface used to access the FPGA is slow. + +This section shows an example of how to write the values listed in +Table~\ref{tbl:multiple-spi} to an 8-bit flash chip starting with address +0. Since there are 10 values to be sent, the transfer can be grouped into +three 3-byte transfers and one one-byte transfer. The code snippet below shows +how these transfers can be performed by writing to the FAR, and +Figure~\ref{fig:multiple-spi} shows the effects of each of the writes. + +\begin{table}[h] + \caption{Values to send to flash chip} + \label{tbl:multiple-spi} + \centerline { + \begin{tabular}{c c c c c c c c c c} + \hline + 0x01 & 0x02 & 0x03 & 0x04 & 0x05 & 0x06 & 0x07 & 0x08 & 0x09 & 0x0a \\ + \hline + \end{tabular} + } +\end{table} + +\begin{lstlisting}[language=C] + FAR = 0x0e030201; + while !(FAR & (1<<28)) + ; + FAR = 0x0e060504; + while !(FAR & (1<<28)) + ; + FAR = 0x0e090807; + while !(FAR & (1<<28)) + ; + FAR = 0x0c00000a; + while !(FAR & (1<<28)) + ; +\end{lstlisting} + +\begin{figure}[h] + \centerline{\includegraphics[scale=1]{fig/multiple-spi}} + \caption{Effects of FAR writes} + \label{fig:multiple-spi} +\end{figure} + +%------------------------------------------------------------------------------ +\end{appendices} + +%============================================================================== +% Bibliography +%============================================================================== +\pagebreak +\bibliographystyle{ieeetr} +\bibliography{wb_xil_multiboot} + +\end{document} diff --git a/modules/common/Manifest.py b/modules/common/Manifest.py index 97f39d646148dc865d03efd17fa8fd53fa9b637b..895b678571774566618b0c2d2ce6eb8a3c88b197 100644 --- a/modules/common/Manifest.py +++ b/modules/common/Manifest.py @@ -11,8 +11,11 @@ files = [ "gencores_pkg.vhd", "gc_pulse_synchronizer.vhd", "gc_pulse_synchronizer2.vhd", "gc_frequency_meter.vhd", - "gc_rr_arbiter.vhd", + "gc_rr_arbiter.vhd", "gc_prio_encoder.vhd", "gc_word_packer.vhd", - "gc_big_adder.vhd" + "gc_i2c_slave.vhd", + "gc_glitch_filt.vhd", + "gc_big_adder.vhd" + ]; diff --git a/modules/common/gc_glitch_filt.vhd b/modules/common/gc_glitch_filt.vhd new file mode 100644 index 0000000000000000000000000000000000000000..b291d8af1dd6ea7eaefdda1e7f66bfd808a2a9ea --- /dev/null +++ b/modules/common/gc_glitch_filt.vhd @@ -0,0 +1,148 @@ +--============================================================================== +-- CERN (BE-CO-HT) +-- Glitch filter with selectable length +--============================================================================== +-- +-- author: Theodor Stana (t.stana@cern.ch) +-- +-- date of creation: 2013-03-12 +-- +-- version: 1.0 +-- +-- description: +-- +-- dependencies: +-- +-- references: +-- +--============================================================================== +-- GNU LESSER GENERAL PUBLIC LICENSE +--============================================================================== +-- This source file is free software; you can redistribute it and/or modify it +-- under the terms of the GNU Lesser General Public License as published by the +-- Free Software Foundation; either version 2.1 of the License, or (at your +-- option) any later version. This source is distributed in the hope that it +-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty +-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +-- See the GNU Lesser General Public License for more details. You should have +-- received a copy of the GNU Lesser General Public License along with this +-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html +--============================================================================== +-- last changes: +-- 2013-03-12 Theodor Stana t.stana@cern.ch File created +--============================================================================== +-- TODO: - +--============================================================================== + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.gencores_pkg.all; + +entity gc_glitch_filt is + generic + ( + -- Length of glitch filter: + -- g_len = 1 => data width should be > 1 clk_i cycle + -- g_len = 2 => data width should be > 2 clk_i cycle + -- etc. + g_len : natural := 4 + ); + port + ( + clk_i : in std_logic; + rst_n_i : in std_logic; + + -- Data input + dat_i : in std_logic; + + -- Data output + -- latency: g_len+1 clk_i cycles + dat_o : out std_logic + ); +end entity gc_glitch_filt; + + +architecture behav of gc_glitch_filt is + + --============================================================================ + -- Component declarations + --============================================================================ + component gc_sync_ffs is + generic( + g_sync_edge : string := "positive" + ); + port( + clk_i : in std_logic; -- clock from the destination clock domain + rst_n_i : in std_logic; -- reset + data_i : in std_logic; -- async input + synced_o : out std_logic; -- synchronized output + npulse_o : out std_logic; -- negative edge detect output (single-clock + -- pulse) + ppulse_o : out std_logic -- positive edge detect output (single-clock + -- pulse) + ); + end component gc_sync_ffs; + + --============================================================================ + -- Signal declarations + --============================================================================ + signal gc_glitch_filt : std_logic_vector(g_len downto 0); + signal dat_synced : std_logic; + +--============================================================================== +-- architecture begin +--============================================================================== +begin + + --============================================================================ + -- Glitch filtration logic + --============================================================================ + -- First, synchronize the data input in the clk_i domain + cmp_sync : gc_sync_ffs + port map + ( + clk_i => clk_i, + rst_n_i => rst_n_i, + data_i => dat_i, + synced_o => dat_synced, + npulse_o => open, + ppulse_o => open + ); + + -- Then, assign the current sample of the glitch filter + gc_glitch_filt(0) <= dat_synced; + + -- Generate glitch filter FFs when the filter length is > 0 + gen_glitch_filt: if (g_len > 0) generate + p_glitch_filt: process (clk_i) + begin + if rising_edge(clk_i) then + if (rst_n_i = '0') then + gc_glitch_filt(g_len downto 1) <= (others => '0'); + else + gc_glitch_filt(g_len downto 1) <= gc_glitch_filt(g_len-1 downto 0); + end if; + end if; + end process p_glitch_filt; + end generate gen_glitch_filt; + + -- and set the data output based on the state of the glitch filter + p_output: process(clk_i) + begin + if rising_edge(clk_i) then + if (rst_n_i = '0') then + dat_o <= '0'; + elsif (gc_glitch_filt = (gc_glitch_filt'range => '1')) then + dat_o <= '1'; + elsif (gc_glitch_filt = (gc_glitch_filt'range => '0')) then + dat_o <= '0'; + end if; + end if; + end process p_output; + +end architecture behav; +--============================================================================== +-- architecture end +--============================================================================== diff --git a/modules/common/gc_i2c_slave.vhd b/modules/common/gc_i2c_slave.vhd new file mode 100644 index 0000000000000000000000000000000000000000..b549e21b7ed7958176b7e34dd62ea0ef7badfeef --- /dev/null +++ b/modules/common/gc_i2c_slave.vhd @@ -0,0 +1,521 @@ +--============================================================================== +-- CERN (BE-CO-HT) +-- I2C slave core +--============================================================================== +-- +-- author: Theodor Stana (t.stana@cern.ch) +-- +-- date of creation: 2013-03-13 +-- +-- version: 1.0 +-- +-- description: +-- +-- Simple I2C slave interface, providing the basic low-level functionality +-- of the I2C protocol. +-- +-- The gc_i2c_slave module waits for a master to initiate a transfer via +-- a start condition. The address is sent next and if the address matches +-- the slave address set via the i2c_addr_i input, the done_p_o output +-- is set. Based on the eighth bit of the first I2C transfer byte, the module +-- then starts shifting in or out each byte in the transfer, setting the +-- done_p_o output after each received/sent byte. +-- +-- For master write (slave read) transfers, the received byte can be read at +-- the rx_byte_o output when the done_p_o pin is high. For master read (slave +-- write) transfers, the slave sends the byte at the tx_byte_i input, which +-- should be set when the done_p_o output is high, either after I2C address +-- reception, or a successful send of a previous byte. +-- +-- dependencies: +-- none. +-- +-- references: +-- [1] The I2C bus specification, version 2.1, NXP Semiconductor, Jan. 2000 +-- http://www.nxp.com/documents/other/39340011.pdf +-- +--============================================================================== +-- GNU LESSER GENERAL PUBLIC LICENSE +--============================================================================== +-- This source file is free software; you can redistribute it and/or modify it +-- under the terms of the GNU Lesser General Public License as published by the +-- Free Software Foundation; either version 2.1 of the License, or (at your +-- option) any later version. This source is distributed in the hope that it +-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty +-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +-- See the GNU Lesser General Public License for more details. You should have +-- received a copy of the GNU Lesser General Public License along with this +-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html +--============================================================================== +-- last changes: +-- 2013-03-13 Theodor Stana t.stana@cern.ch File created +--============================================================================== +-- TODO: +-- - Stop condition +--============================================================================== + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.gencores_pkg.all; + +entity gc_i2c_slave is + port + ( + -- Clock, reset ports + clk_i : in std_logic; + rst_n_i : in std_logic; + + -- I2C lines + scl_i : in std_logic; + scl_o : out std_logic; + scl_en_o : out std_logic; + sda_i : in std_logic; + sda_o : out std_logic; + sda_en_o : out std_logic; + + -- Slave address + i2c_addr_i : in std_logic_vector(6 downto 0); + + -- ACK input, should be set after done_p_o = '1' + -- (note that the bit is reversed wrt I2C ACK bit) + -- '1' - ACK + -- '0' - NACK + i2c_ack_i : in std_logic; + + -- I2C bus operation, set after address detection + -- '0' - write + -- '1' - read + op_o : out std_logic; + + -- Byte to send, should be loaded while done_p_o = '1' + tx_byte_i : in std_logic_vector(7 downto 0); + + -- Received byte, valid after done_p_o = '1' + rx_byte_o : out std_logic_vector(7 downto 0); + + -- Done pulse signal, valid when + -- * received address matches i2c_addr_i, signaling valid op_o; + -- * a byte was received, signaling valid rx_byte_o and an ACK/NACK should be + -- sent to master; + -- * sent a byte, should set tx_byte_i. + done_p_o : out std_logic; + + -- I2C transfer state + -- "00" - Idle + -- "01" - Got address, matches i2c_addr_i + -- "10" - Read done, waiting ACK/NACK + -- "11" - Write done, waiting next byte + stat_o : out std_logic_vector(1 downto 0) + ); +end entity gc_i2c_slave; + + +architecture behav of gc_i2c_slave is + + --============================================================================ + -- Type declarations + --============================================================================ + type t_state is + ( + IDLE, -- idle + STA, -- start condition received + ADDR, -- shift in I2C address bits + ADDR_ACK, -- ACK/NACK to I2C address + RD, -- shift in byte to read + RD_ACK, -- ACK/NACK to received byte + WR_LOAD_TXSR, -- load byte to send via I2C + WR, -- shift out byte + WR_ACK -- get ACK/NACK from master + ); + + --============================================================================ + -- Signal declarations + --============================================================================ + -- Deglitched signals and delays for SCL and SDA lines + signal scl_deglitched : std_logic; + signal scl_deglitched_d0 : std_logic; + signal sda_deglitched : std_logic; + signal sda_deglitched_d0 : std_logic; + signal scl_r_edge_p : std_logic; + signal scl_f_edge_p : std_logic; + signal sda_f_edge_p : std_logic; + signal sda_r_edge_p : std_logic; + + -- FSM + signal state : t_state; + + -- FSM tick + signal tick_p : std_logic; + signal tick_cnt : std_logic_vector(5 downto 0); + + -- RX and TX shift registers + signal txsr : std_logic_vector(7 downto 0); + signal rxsr : std_logic_vector(7 downto 0); + + -- Bit counter on RX & TX + signal bit_cnt : unsigned(2 downto 0); + + -- Watchdog counter signals + signal watchdog_cnt : unsigned(26 downto 0); + signal watchdog_rst : std_logic; + signal rst_fr_watchdog : std_logic; + +--============================================================================== +-- architecture begin +--============================================================================== +begin + + --============================================================================ + -- I/O logic + --============================================================================ + -- No clock stretching implemented, always disable SCL line + scl_o <= '0'; + scl_en_o <= '0'; + + -- SDA line driven low; SDA_EN line controls when the tristate buffer is enabled + sda_o <= '0'; + + -- Assign RX byte output + rx_byte_o <= rxsr; + + --============================================================================ + -- Deglitching logic + --============================================================================ + -- Generate deglitched SCL signal with 54-ns max. glitch width + cmp_scl_deglitch : gc_glitch_filt + generic map + ( + g_len => 7 + ) + port map + ( + clk_i => clk_i, + rst_n_i => rst_n_i, + dat_i => scl_i, + dat_o => scl_deglitched + ); + + -- and create a delayed version of this signal, together with one-tick-long + -- falling-edge detection signal + p_scl_degl_d0 : process(clk_i) is + begin + if rising_edge(clk_i) then + if (rst_n_i = '0') then + scl_deglitched_d0 <= '0'; + scl_f_edge_p <= '0'; + scl_r_edge_p <= '0'; + else + scl_deglitched_d0 <= scl_deglitched; + scl_f_edge_p <= (not scl_deglitched) and scl_deglitched_d0; + scl_r_edge_p <= scl_deglitched and (not scl_deglitched_d0); + end if; + end if; + end process p_scl_degl_d0; + + -- Generate deglitched SDA signal with 54-ns max. glitch width + cmp_sda_deglitch : gc_glitch_filt + generic map + ( + g_len => 7 + ) + port map + ( + clk_i => clk_i, + rst_n_i => rst_n_i, + dat_i => sda_i, + dat_o => sda_deglitched + ); + + -- and create a delayed version of this signal, together with one-tick-long + -- falling- and rising-edge detection signals + p_sda_deglitched_d0 : process(clk_i) is + begin + if rising_edge(clk_i) then + if (rst_n_i = '0') then + sda_deglitched_d0 <= '0'; + sda_f_edge_p <= '0'; + sda_r_edge_p <= '0'; + else + sda_deglitched_d0 <= sda_deglitched; + sda_f_edge_p <= (not sda_deglitched) and sda_deglitched_d0; + sda_r_edge_p <= sda_deglitched and (not sda_deglitched_d0); + end if; + end if; + end process p_sda_deglitched_d0; + + --============================================================================ + -- Tick generation + --============================================================================ +-- p_tick : process (clk_i) is +-- begin +-- if rising_edge(clk_i) then +-- if (rst_n_i = '0') then +-- tick_cnt <= '0'; +-- tick_p <= '0'; +-- elsif (scl_f_edge_p = '1') then +-- tick_en <= '1'; +-- else +-- if (tick_en = '1') then +-- tick_cnt <= tick_cnt + 1; +-- tick_p <= '0'; +-- if (tick_cnt = (tick_cnt'range => '1')) then +-- tick_p <= '1'; +-- tick_en <= '0'; +-- end if; +-- else +-- tick_p <= '0'; +-- end if; +-- end if; +-- end if; +-- end process p_tick; + + --============================================================================ + -- FSM logic + --============================================================================ + p_fsm: process (clk_i) is + begin + if rising_edge(clk_i) then + if (rst_n_i = '0') or (rst_fr_watchdog = '1') then + state <= IDLE; + watchdog_rst <= '1'; + bit_cnt <= (others => '0'); + rxsr <= (others => '0'); + txsr <= (others => '0'); + sda_en_o <= '0'; + done_p_o <= '0'; + op_o <= '0'; + stat_o <= c_i2cs_idle; + + -- I2C start condition + elsif (sda_f_edge_p = '1') and (scl_deglitched = '1') then + state <= ADDR; + bit_cnt <= (others => '0'); + watchdog_rst <= '0'; + + -- I2C stop condition + elsif (sda_r_edge_p = '1') and (scl_deglitched = '1') then + state <= IDLE; + done_p_o <= '1'; + stat_o <= c_i2cs_idle; + + -- state machine logic + else + case state is + --------------------------------------------------------------------- + -- IDLE + --------------------------------------------------------------------- + -- When idle, outputs and bit counters are cleared, while waiting + -- for a start condition. + --------------------------------------------------------------------- + when IDLE => + bit_cnt <= (others => '0'); + sda_en_o <= '0'; + done_p_o <= '0'; + watchdog_rst <= '1'; + stat_o <= c_i2cs_idle; + +-- --------------------------------------------------------------------- +-- -- STA +-- --------------------------------------------------------------------- +-- -- When a start condition is received, the bit counter gets cleared +-- -- to prepare for receiving the address byte. On the falling edge of +-- -- SCL, we go into the address state. +-- --------------------------------------------------------------------- +-- when STA => +-- bit_cnt <= (others => '0'); +-- if (scl_f_edge_p = '1') then +-- state <= ADDR; +-- end if; + + --------------------------------------------------------------------- + -- ADDR + --------------------------------------------------------------------- + -- Shift in the seven address bits and the R/W bit, and go to address + -- acknowledgement. When the eighth bit has been shifted in, check + -- if address is ours and signal to external module. Then, go to + -- ADDR_ACK state. + --------------------------------------------------------------------- + when ADDR => + -- Shifting in is done on rising edge of SCL + if (scl_r_edge_p = '1') then + rxsr <= rxsr(6 downto 0) & sda_deglitched; + bit_cnt <= bit_cnt + 1; + + -- Shifted in 8 bits, go to ADDR_ACK. Check to see if received + -- address is ours and set op_o if so. + if (bit_cnt = 7) then + state <= ADDR_ACK; + if (rxsr(6 downto 0) = i2c_addr_i) then + op_o <= sda_deglitched; + done_p_o <= '1'; + stat_o <= c_i2cs_addr_good; + end if; + end if; + end if; + + --------------------------------------------------------------------- + -- ADDR_ACK + --------------------------------------------------------------------- + -- Here, we check to see if the address is ours and ACK/NACK + -- accordingly. The next action is dependent upon the state of the + -- R/W bit received via I2C. + --------------------------------------------------------------------- + when ADDR_ACK => + -- Clear done pulse + done_p_o <= '0'; + + -- we write the ACK bit, so enable output + sda_en_o <= i2c_ack_i; + + -- If the received address is ours, send the ACK set by external + -- module and, on the falling edge of SCL, go to appropriate state + -- based on R/W bit. + if (rxsr(7 downto 1) = i2c_addr_i) then + if (scl_f_edge_p = '1') then + sda_en_o <= '0'; + if (rxsr(0) = '0') then + state <= RD; + else + state <= WR_LOAD_TXSR; + end if; + end if; + -- If received address is not ours, NACK and go back to IDLE + else + sda_en_o <= '0'; + state <= IDLE; + end if; + + --------------------------------------------------------------------- + -- RD + --------------------------------------------------------------------- + -- Shift in bits sent by the master. + --------------------------------------------------------------------- + when RD => + -- Shifting occurs on falling edge of SCL + if (scl_f_edge_p = '1') then + rxsr <= rxsr(6 downto 0) & sda_deglitched; + bit_cnt <= bit_cnt + 1; + + -- Received 8 bits, go to RD_ACK and signal external module + if (bit_cnt = 7) then + state <= RD_ACK; + done_p_o <= '1'; + stat_o <= c_i2cs_rd_done; + end if; + end if; + + --------------------------------------------------------------------- + -- RD_ACK + --------------------------------------------------------------------- + -- Send ACK/NACK, as received from external command + --------------------------------------------------------------------- + when RD_ACK => + -- Clear done pulse + done_p_o <= '0'; + + -- we write the ACK bit, so enable output and send the ACK bit + sda_en_o <= i2c_ack_i; + + -- based on the ACK received by external command, we read the next + -- bit (ACK) or go back to idle state (NACK) + if (scl_f_edge_p = '1') then + sda_en_o <= '0'; + if (i2c_ack_i = '1') then + state <= RD; + else + state <= IDLE; + end if; + end if; + + --------------------------------------------------------------------- + -- WR_LOAD_TXSR + --------------------------------------------------------------------- + -- Load TXSR with the input value. + --------------------------------------------------------------------- + when WR_LOAD_TXSR => + txsr <= tx_byte_i; + state <= WR; + + --------------------------------------------------------------------- + -- WR + --------------------------------------------------------------------- + -- Shift out the eight bits of TXSR. + --------------------------------------------------------------------- + when WR => + -- slave writes, so enable output + sda_en_o <= txsr(7); + + -- Shift TXSR on falling edge of SCL + if (scl_f_edge_p = '1') then + txsr <= txsr(6 downto 0) & '0'; + bit_cnt <= bit_cnt + 1; + + -- Eight bits sent, disable SDA end go to WR_ACK + if (bit_cnt = 7) then + sda_en_o <= '0'; + state <= WR_ACK; + done_p_o <= '1'; + stat_o <= c_i2cs_wr_done; + end if; + end if; + + --------------------------------------------------------------------- + -- WR_ACK + --------------------------------------------------------------------- + -- The master drives the ACK bit here, so on the falling edge of + -- SCL, we check the ack bit. A '0' (ACK) means more bits should be sent, + -- so we load the next value of the TXSR. A '1' (NACK) means the + -- master is done reading and a STO follows, so we go back to IDLE + -- state. + --------------------------------------------------------------------- + when WR_ACK => + done_p_o <= '0'; + if (scl_f_edge_p = '1') then + if (sda_deglitched = '0') then + state <= WR_LOAD_TXSR; + else + state <= IDLE; + end if; + end if; + + --------------------------------------------------------------------- + -- Any other state: go back to idle. + --------------------------------------------------------------------- + when others => + state <= IDLE; + + end case; + end if; + end if; + end process p_fsm; + + --============================================================================ + -- Watchdog counter process + -- Resets the FSM after one second. The watchdog_rst signal is controlled by + -- the FSM and resets the watchdog if the I2C master still controls the + -- slave, signaled by the SCL line going low. If for one second the master + -- does not toggle the SCL line, the FSM gets reset. + --============================================================================ + p_watchdog: process(clk_i) + begin + if rising_edge(clk_i) then + if (rst_n_i = '0') or (watchdog_rst = '1') then + watchdog_cnt <= (others => '0'); + rst_fr_watchdog <= '0'; + else + watchdog_cnt <= watchdog_cnt + 1; + rst_fr_watchdog <= '0'; + if (watchdog_cnt = 124999999) then + watchdog_cnt <= (others => '0'); + rst_fr_watchdog <= '1'; + end if; + end if; + end if; + end process p_watchdog; + +end architecture behav; +--============================================================================== +-- architecture end +--============================================================================== diff --git a/modules/common/gencores_pkg.vhd b/modules/common/gencores_pkg.vhd index c1b1aa75d84dd4450987d41ac11f313e7d0879ee..ad09c551d603abe54bd01de0cdfc839d7c6bd5ff 100644 --- a/modules/common/gencores_pkg.vhd +++ b/modules/common/gencores_pkg.vhd @@ -172,7 +172,7 @@ package gencores_pkg is d_p_i : in std_logic; q_p_o : out std_logic); end component; - + component gc_frequency_meter generic ( g_with_internal_timebase : boolean; @@ -257,19 +257,102 @@ package gencores_pkg is c2_o : out std_logic); end component; + ------------------------------------------------------------------------------ + -- I2C slave + ------------------------------------------------------------------------------ + constant c_i2cs_idle : std_logic_vector(1 downto 0) := "00"; + constant c_i2cs_addr_good : std_logic_vector(1 downto 0) := "01"; + constant c_i2cs_rd_done : std_logic_vector(1 downto 0) := "10"; + constant c_i2cs_wr_done : std_logic_vector(1 downto 0) := "11"; + + component gc_i2c_slave is + port + ( + -- Clock, reset ports + clk_i : in std_logic; + rst_n_i : in std_logic; + + -- I2C lines + scl_i : in std_logic; + scl_o : out std_logic; + scl_en_o : out std_logic; + sda_i : in std_logic; + sda_o : out std_logic; + sda_en_o : out std_logic; + + -- Slave address + i2c_addr_i : in std_logic_vector(6 downto 0); + + -- ACK input, should be set after done_p_o = '1' + -- (note that the bit is reversed wrt I2C ACK bit) + -- '1' - ACK + -- '0' - NACK + i2c_ack_i : in std_logic; + + -- I2C bus operation, set after address detection + -- '0' - write + -- '1' - read + op_o : out std_logic; + + -- Byte to send, should be loaded while done_p_o = '1' + tx_byte_i : in std_logic_vector(7 downto 0); + + -- Received byte, valid after done_p_o = '1' + rx_byte_o : out std_logic_vector(7 downto 0); + + -- Done pulse signal, valid when + -- * received address matches i2c_addr_i, signaling valid op_o; + -- * a byte was received, signaling valid rx_byte_o and an ACK/NACK should be + -- sent to master; + -- * sent a byte, should set tx_byte_i. + done_p_o : out std_logic; + + -- I2C transfer state + -- "00" - Idle + -- "01" - Got address, matches i2c_addr_i + -- "10" - Read done, waiting ACK/NACK + -- "11" - Write done, waiting next byte + stat_o : out std_logic_vector(1 downto 0) + ); + end component gc_i2c_slave; + + ------------------------------------------------------------------------------ + -- Glitch filter + ------------------------------------------------------------------------------ + component gc_glitch_filt is + generic + ( + -- Length of glitch filter: + -- g_len = 1 => data width should be > 1 clk_i cycle + -- g_len = 2 => data width should be > 2 clk_i cycle + -- etc. + g_len : natural := 4 + ); + port + ( + clk_i : in std_logic; + rst_n_i : in std_logic; + + -- Data input + dat_i : in std_logic; + + -- Data output + -- latency: g_len+1 clk_i cycles + dat_o : out std_logic + ); + end component gc_glitch_filt; + + + --============================================================================ + -- Procedures + --============================================================================ procedure f_rr_arbitrate ( procedure f_rr_arbitrate ( signal req : in std_logic_vector; signal pre_grant : in std_logic_vector; signal grant : out std_logic_vector); - function f_big_ripple(a, b : std_logic_vector; c : std_logic) return std_logic_vector; - function f_gray_encode(x : std_logic_vector) return std_logic_vector; - function f_gray_decode(x : std_logic_vector; step : natural) return std_logic_vector; - end package; - - package body gencores_pkg is -- Simple round-robin arbiter: diff --git a/modules/wishbone/Manifest.py b/modules/wishbone/Manifest.py index 50919cf9cfbed306687bc037031c4ffe79ee2925..11c93159462e346faa034c1df2ad27d22456ed16 100644 --- a/modules/wishbone/Manifest.py +++ b/modules/wishbone/Manifest.py @@ -19,6 +19,7 @@ modules = { "local" : [ "wb_serial_lcd", "wb_spi_flash", "wb_simple_pwm", + "wb_i2c_bridge", "wbgen2" ]} diff --git a/modules/wishbone/wb_i2c_bridge/Manifest.py b/modules/wishbone/wb_i2c_bridge/Manifest.py new file mode 100644 index 0000000000000000000000000000000000000000..50f4758fecf8d0cce1cfca73de4779ef6349b3c3 --- /dev/null +++ b/modules/wishbone/wb_i2c_bridge/Manifest.py @@ -0,0 +1,4 @@ +files = [ + "wb_i2c_bridge.vhd" + ] + diff --git a/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd b/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd new file mode 100644 index 0000000000000000000000000000000000000000..f168dfb24baba007ba4b1e043f1b2157e680f9bf --- /dev/null +++ b/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd @@ -0,0 +1,431 @@ +--============================================================================== +-- CERN (BE-CO-HT) +-- VME Board Control Protocol (VBCP) to Wishbone bridge for VME64x crates +--============================================================================== +-- +-- author: Theodor Stana (t.stana@cern.ch) +-- +-- date of creation: 2013-02-15 +-- +-- version: 1.0 +-- +-- description: +-- This module implements an I2C to Wishbone bridge for VME64x crates, +-- following the protocol defined in [1]. It uses a low-level I2C slave module +-- reacting to transfers initiated by an I2C master, in this case, a VME64x +-- system monitor (SysMon) [2]. +-- +-- The I2C slave module sets its done_p_o pin high when the I2C address received +-- from the SysMon corresponds to the slave address and every time a byte has +-- been received or sent correctly. The done_p_o pin of the slave module is +-- de-asserted when the slave performs a transfer. +-- +-- The bridge module employs a state machine that checks for low-to-high +-- transitions in the slave done_p_o pin and shifts bytes in and out over I2C +-- to implement the protocol defined in [1]. +-- +-- dependencies: +-- none. +-- +-- references: +-- [1] ELMA SNMP Specification +-- http://www.ohwr.org/documents/227 +-- [2] System Monitor's Users Manual +-- http://www.ohwr.org/documents/226 +-- +--============================================================================== +-- GNU LESSER GENERAL PUBLIC LICENSE +--============================================================================== +-- This source file is free software; you can redistribute it and/or modify it +-- under the terms of the GNU Lesser General Public License as published by the +-- Free Software Foundation; either version 2.1 of the License, or (at your +-- option) any later version. This source is distributed in the hope that it +-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty +-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +-- See the GNU Lesser General Public License for more details. You should have +-- received a copy of the GNU Lesser General Public License along with this +-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html +--============================================================================== +-- last changes: +-- 2013-02-28 Theodor Stana t.stana@cern.ch File created +--============================================================================== +-- TODO: - +--============================================================================== + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.gencores_pkg.all; + +entity wb_i2c_bridge is + port + ( + -- Clock, reset + clk_i : in std_logic; + rst_n_i : in std_logic; + + -- I2C lines + sda_en_o : out std_logic; + sda_i : in std_logic; + sda_o : out std_logic; + scl_en_o : out std_logic; + scl_i : in std_logic; + scl_o : out std_logic; + + -- I2C address + i2c_addr_i : in std_logic_vector(6 downto 0); + + -- Transfer In Progress (TIP) and Error outputs + -- TIP : '1' when the I2C slave detects a matching I2C address, thus a + -- transfer is in progress + -- '0' when idle + -- ERR : '1' when the SysMon attempts to access an invalid WB slave + -- '0' when idle + tip_o : out std_logic; + err_o : out std_logic; + + -- Wishbone master signals + wbm_stb_o : out std_logic; + wbm_cyc_o : out std_logic; + wbm_sel_o : out std_logic_vector(3 downto 0); + wbm_we_o : out std_logic; + wbm_dat_i : in std_logic_vector(31 downto 0); + wbm_dat_o : out std_logic_vector(31 downto 0); + wbm_adr_o : out std_logic_vector(31 downto 0); + wbm_ack_i : in std_logic; + wbm_rty_i : in std_logic; + wbm_err_i : in std_logic + ); +end entity wb_i2c_bridge; + +architecture behav of wb_i2c_bridge is + + --============================================================================ + -- Type declarations + --============================================================================ + type t_state is + ( + IDLE, -- idle state + SYSMON_WB_ADR, -- get the WB register address + SIM_WB_TRANSF, -- simulate a WB transfer with the received address + OPER, -- operation to perform on the WB register + SYSMON_RD_WB, -- perform a WB read transfer, for sending word to the SysMon + SYSMON_RD, -- send the word to the SysMon during read transfer + SYSMON_WR, -- read the word sent by the SysMon during write transfer + SYSMON_WR_WB -- perform a WB write transfer, storing the received word + ); + + --============================================================================ + -- Signal declarations + --============================================================================ + -- Slave component signals + signal i2c_ack : std_logic; + signal op : std_logic; + signal start_op : std_logic; + signal tx_byte : std_logic_vector(7 downto 0); + signal rx_byte : std_logic_vector(7 downto 0); + signal done : std_logic; + signal done_d0 : std_logic; + signal stat : std_logic_vector(1 downto 0); + + -- Wishbone temporary signals + signal wb_dat_out : std_logic_vector(31 downto 0); + signal wb_dat_in : std_logic_vector(31 downto 0); + signal wb_adr : std_logic_vector(15 downto 0); + signal wb_cyc : std_logic; + signal wb_stb : std_logic; + signal wb_we : std_logic; + signal wb_ack : std_logic; + signal wb_err : std_logic; + signal wb_rty : std_logic; + + -- FSM control signals + signal state : t_state; + signal dat_byte_cnt : unsigned(1 downto 0); + signal adr_byte_cnt : unsigned(0 downto 0); + +begin + + --============================================================================ + -- Slave component instantiation and connection + --============================================================================ + cmp_i2c_slave: gc_i2c_slave + port map + ( + clk_i => clk_i, + rst_n_i => rst_n_i, + + -- I2C lines + scl_i => scl_i, + scl_o => scl_o, + scl_en_o => scl_en_o, + sda_i => sda_i, + sda_o => sda_o, + sda_en_o => sda_en_o, + + -- Slave address + i2c_addr_i => i2c_addr_i, + + -- ACK input, should be set after done_p_o = '1' + -- '0' - ACK + -- '1' - NACK + i2c_ack_i => i2c_ack, + + -- I2C bus operation, set after address detection + -- '0' - write + -- '1' - read + op_o => op, + + -- Byte to send, should be loaded while done_p_o = '1' + tx_byte_i => tx_byte, + + -- Received byte, valid after done_p_o = '1' + rx_byte_o => rx_byte, + + -- Done signal, valid when + -- * received address matches i2c_addr_i, signaling valid op_o; + -- * a byte was received, signaling valid rx_byte_o and an ACK/NACK should be + -- sent to master; + -- * sent a byte, should set tx_byte_i. + done_p_o => done, + + stat_o => stat + ); + + --============================================================================ + -- I2C to Wishbone bridge FSM logic + --============================================================================ + -- First, assign Wishbone outputs + wbm_dat_o <= wb_dat_out; + wbm_adr_o <= x"0000" & wb_adr; + wbm_cyc_o <= wb_cyc; + wbm_stb_o <= wb_stb; + wbm_we_o <= wb_we; + wbm_sel_o <= (others => '1'); + + -- Next, assign some Wishbone inputs to internal signals + wb_ack <= wbm_ack_i; + wb_err <= wbm_err_i; + wb_rty <= wbm_rty_i; + + -- Then, assign the I2C byte to TX to the first byte of the internal WB input + -- data signal; shifting is handled inside the FSM. + tx_byte <= wb_dat_in(7 downto 0); + + + -- Finally, the FSM logic + p_fsm: process (clk_i) is + begin + if rising_edge(clk_i) then + if (rst_n_i = '0') then + state <= IDLE; + wb_adr <= (others => '0'); + wb_dat_out <= (others => '0'); + wb_dat_in <= (others => '0'); + wb_cyc <= '0'; + wb_stb <= '0'; + wb_we <= '0'; + start_op <= '0'; + i2c_ack <= '0'; + tip_o <= '0'; + err_o <= '0'; + adr_byte_cnt <= (others => '0'); + dat_byte_cnt <= (others => '0'); + + else + case state is + --------------------------------------------------------------------- + -- IDLE + --------------------------------------------------------------------- + -- After the slave acknowledges its I2C address, the register address + -- bytes have to be shifted in. The start-of-transfer operation + -- is also stored here, to check versus the third I2C transfer in + -- the protocol. At this point, since the SysMon writes the WB + -- address, start_op will be '0' (write). + --------------------------------------------------------------------- + when IDLE => + err_o <= '0'; + tip_o <= '0'; + i2c_ack <= '0'; + dat_byte_cnt <= (others => '0'); + if (done = '1') and (stat = c_i2cs_addr_good) then + tip_o <= '1'; + i2c_ack <= '1'; + state <= SYSMON_WB_ADR; + start_op <= op; + end if; + + --------------------------------------------------------------------- + -- SYSMON_WB_ADR + --------------------------------------------------------------------- + -- Shift in the two address bytes sent by the SysMon and ACK each of + -- them. The second byte's ACK is also controlled by the next state. + --------------------------------------------------------------------- + when SYSMON_WB_ADR => + if (done = '1') then + if (stat = c_i2cs_rd_done) then + wb_adr <= wb_adr(7 downto 0) & rx_byte; + i2c_ack <= '1'; + adr_byte_cnt <= adr_byte_cnt + 1; + if (adr_byte_cnt = 1) then + state <= SIM_WB_TRANSF; + end if; + else + i2c_ack <= '0'; + state <= IDLE; + end if; + end if; + + --------------------------------------------------------------------- + -- SIM_WB_TRANSF + --------------------------------------------------------------------- + -- Simulate a Wishbone transfer with the received address and go + -- to operation state if we get a WB ACK, or back to idle if we get + -- a WB error. In the latter case, an NACK is sent to the SysMon. + --------------------------------------------------------------------- + when SIM_WB_TRANSF => + wb_cyc <= '1'; + wb_stb <= '1'; + if (wb_ack = '1') then + i2c_ack <= '1'; + wb_cyc <= '0'; + wb_stb <= '0'; + state <= OPER; + elsif (wb_err = '1') then + err_o <= '1'; + i2c_ack <= '0'; + wb_cyc <= '0'; + wb_stb <= '0'; + state <= IDLE; + end if; + + --------------------------------------------------------------------- + -- OPER + --------------------------------------------------------------------- + -- This is the third I2C transfer occuring in the protocol. At this + -- point, the first byte of a SysMon write transfer is sent, or a + -- restart, I2C slave address and read bit are sent to signal a + -- SysMon read transfer. + -- + -- So, here we shift in the received byte in case of a SysMon write + -- transfer and then check the OP signal. This is set by the slave + -- while it is in its I2C address read state and will be different + -- from the starting case if a read transfer ('1') occurs. + -- + -- If a read transfer follows, the data byte counter and WB data + -- output are cleared to avoid conflicts with future transfers. + --------------------------------------------------------------------- + when OPER => + if (done = '1') then + if (stat = c_i2cs_rd_done) then + wb_dat_out <= rx_byte & wb_dat_out(31 downto 8); + dat_byte_cnt <= dat_byte_cnt + 1; + i2c_ack <= '1'; + state <= SYSMON_WR; + elsif (stat = c_i2cs_addr_good) and (op /= start_op) then + i2c_ack <= '1'; + state <= SYSMON_RD_WB; + else + i2c_ack <= '0'; + state <= IDLE; + end if; + end if; + + --------------------------------------------------------------------- + -- SYSMON_WR + --------------------------------------------------------------------- + -- During write transfers, each byte is shifted in, until all bytes + -- in the transfer have been sent. When this has occured, a Wishbone + -- write transfer is initiated in the next state. + --------------------------------------------------------------------- + when SYSMON_WR => + if (done = '1') then + if (stat = c_i2cs_rd_done) then + wb_dat_out <= rx_byte & wb_dat_out(31 downto 8); + dat_byte_cnt <= dat_byte_cnt + 1; + i2c_ack <= '1'; + if (dat_byte_cnt = 3) then + state <= SYSMON_WR_WB; + end if; + else + i2c_ack <= '0'; + state <= IDLE; + end if; + end if; + + --------------------------------------------------------------------- + -- SYSMON_WR_WB + --------------------------------------------------------------------- + -- Perform a write transfer over Wishbone bus with the received + -- data word. + --------------------------------------------------------------------- + when SYSMON_WR_WB => + wb_cyc <= '1'; + wb_stb <= '1'; + wb_we <= '1'; + if (wb_ack = '1') then -- or (wb_err = '1') then + wb_cyc <= '0'; + wb_stb <= '0'; + wb_we <= '0'; + state <= SYSMON_WR; --IDLE; + elsif (wb_err = '1') then + err_o <= '1'; + state <= IDLE; + end if; + + --------------------------------------------------------------------- + -- SYSMON_RD_WB + --------------------------------------------------------------------- + -- This state is reached from the operation state; here, we perform + -- a read transfer on the Wishbone bus to prepare the data that + -- should be sent to the SysMon. If the WB address is incorrect, we + -- go back to the IDLE state. + --------------------------------------------------------------------- + when SYSMON_RD_WB => + wb_cyc <= '1'; + wb_stb <= '1'; + if (wb_ack = '1') then + wb_dat_in <= wbm_dat_i; + wb_cyc <= '0'; + wb_stb <= '0'; + state <= SYSMON_RD; + elsif (wb_err = '1') then + err_o <= '1'; + wb_cyc <= '0'; + wb_stb <= '0'; + state <= IDLE; + end if; + + --------------------------------------------------------------------- + -- SYSMON_RD + --------------------------------------------------------------------- + -- Shift out the bytes over I2C and go back to IDLE state. + --------------------------------------------------------------------- + when SYSMON_RD => + if (done = '1') then + if (stat = c_i2cs_wr_done) then + wb_dat_in <= x"00" & wb_dat_in(31 downto 8); + dat_byte_cnt <= dat_byte_cnt + 1; + i2c_ack <= '1'; + if (dat_byte_cnt = 3) then + state <= IDLE; + end if; + else + i2c_ack <= '0'; + state <= IDLE; + end if; + end if; + + --------------------------------------------------------------------- + -- Any other state: go back to idle. + --------------------------------------------------------------------- + when others => + state <= IDLE; + + end case; + end if; + end if; + end process p_fsm; + +end behav; diff --git a/modules/wishbone/wishbone_pkg.vhd b/modules/wishbone/wishbone_pkg.vhd index 9560c3139343be9989f5b81a0dc8d0b70d5b4a76..42228b582e2d2a5320eb2530142bed9fc2577024 100644 --- a/modules/wishbone/wishbone_pkg.vhd +++ b/modules/wishbone/wishbone_pkg.vhd @@ -899,6 +899,50 @@ package wishbone_pkg is external_granted_o : out std_logic); end component; + ----------------------------------------------------------------------------- + -- I2C to Wishbone bridge, following protocol defined with ELMA + ----------------------------------------------------------------------------- + component wb_i2c_bridge is + port + ( + -- Clock, reset + clk_i : in std_logic; + rst_n_i : in std_logic; + + -- I2C lines + sda_en_o : out std_logic; + sda_i : in std_logic; + sda_o : out std_logic; + scl_en_o : out std_logic; + scl_i : in std_logic; + scl_o : out std_logic; + + -- I2C address + i2c_addr_i : in std_logic_vector(6 downto 0); + + -- Transfer In Progress (TIP) and Error outputs + -- TIP : '1' when the I2C slave detects a matching I2C address, thus a + -- transfer is in progress + -- '0' when idle + -- ERR : '1' when the SysMon attempts to access an invalid WB slave + -- '0' when idle + tip_o : out std_logic; + err_o : out std_logic; + + -- Wishbone master signals + wbm_stb_o : out std_logic; + wbm_cyc_o : out std_logic; + wbm_sel_o : out std_logic_vector(3 downto 0); + wbm_we_o : out std_logic; + wbm_dat_i : in std_logic_vector(31 downto 0); + wbm_dat_o : out std_logic_vector(31 downto 0); + wbm_adr_o : out std_logic_vector(31 downto 0); + wbm_ack_i : in std_logic; + wbm_rty_i : in std_logic; + wbm_err_i : in std_logic + ); + end component wb_i2c_bridge; + end wishbone_pkg; package body wishbone_pkg is diff --git a/platform/xilinx/Manifest.py b/platform/xilinx/Manifest.py index 23e787c4d6bffd26a661c0f2a209ec79925528da..24365cb02b3845625ec7c025d0afe4ff760249a7 100644 --- a/platform/xilinx/Manifest.py +++ b/platform/xilinx/Manifest.py @@ -1 +1,6 @@ -modules = { "local" : [ "wb_xilinx_fpga_loader" ] } +modules = { + "local" : [ + "wb_xilinx_fpga_loader", + "wb_xil_multiboot" + ] +} diff --git a/platform/xilinx/wb_xil_multiboot/Manifest.py b/platform/xilinx/wb_xil_multiboot/Manifest.py new file mode 100644 index 0000000000000000000000000000000000000000..4e8263f401be47b07adc1682b7755787d4e508ce --- /dev/null +++ b/platform/xilinx/wb_xil_multiboot/Manifest.py @@ -0,0 +1,6 @@ +files = [ + "spi_master.vhd", + "multiboot_fsm.vhd", + "multiboot_regs.vhd", + "wb_xil_multiboot.vhd" + ] diff --git a/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd b/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd new file mode 100644 index 0000000000000000000000000000000000000000..34a0a297fe4fe9b1537cbfcaef891bf1476e2200 --- /dev/null +++ b/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd @@ -0,0 +1,495 @@ +--============================================================================== +-- CERN (BE-CO-HT) +-- Xilinx MultiBoot FSM +--============================================================================== +-- +-- author: Theodor Stana (t.stana@cern.ch) +-- +-- date of creation: 2013-08-19 +-- +-- version: 1.0 +-- +-- description: +-- The finite-state machine (FSM) module for the xil_multiboot module. Based +-- on input received from the MultiBoot module registers, it starts one of +-- three sequences: +-- - SPI -- shift out up to three bytes (based on the NBYTES) +-- value in FAR +-- - RDCFGREG -- read a configuration register from the Xilinx FPGA +-- configuration logic +-- - IPROG -- issue an IPROG command to the Xilinx FPGA configuration +-- logic +-- +-- references: +-- [1] Xilinx UG380 Spartan-6 FPGA Configuration Guide v2.5 +-- http://www.xilinx.com/support/documentation/user_guides/ug380.pdf +-- +--============================================================================== +-- GNU LESSER GENERAL PUBLIC LICENSE +--============================================================================== +-- This source file is free software; you can redistribute it and/or modify it +-- under the terms of the GNU Lesser General Public License as published by the +-- Free Software Foundation; either version 2.1 of the License, or (at your +-- option) any later version. This source is distributed in the hope that it +-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty +-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +-- See the GNU Lesser General Public License for more details. You should have +-- received a copy of the GNU Lesser General Public License along with this +-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html +--============================================================================== +-- last changes: +-- 2013-08-19 Theodor Stana t.stana@cern.ch File created +--============================================================================== +-- TODO: - +--============================================================================== + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +entity multiboot_fsm is + port + ( + -- Clock and reset inputs + clk_i : in std_logic; + rst_n_i : in std_logic; + + -- Control register inputs + reg_rdcfgreg_i : in std_logic; + reg_cfgregadr_i : in std_logic_vector(5 downto 0); + reg_iprog_i : in std_logic; + + -- Multiboot and golden bitstream start addresses + reg_gbbar_i : in std_logic_vector(31 downto 0); + reg_mbbar_i : in std_logic_vector(31 downto 0); + + -- Outputs to status register + reg_cfgreg_img_o : out std_logic_vector(15 downto 0); + reg_cfgreg_valid_o : out std_logic; + + -- Flash access register signals + reg_far_data_i : in std_logic_vector(23 downto 0); + reg_far_data_o : out std_logic_vector(23 downto 0); + reg_far_nbytes_i : in std_logic_vector(1 downto 0); + reg_far_xfer_i : in std_logic; + reg_far_cs_i : in std_logic; + reg_far_ready_o : out std_logic; + + -- SPI master signals + spi_xfer_o : out std_logic; + spi_cs_o : out std_logic; + spi_data_i : in std_logic_vector(7 downto 0); + spi_data_o : out std_logic_vector(7 downto 0); + spi_ready_i : in std_logic; + + -- Ports for the external ICAP component + icap_dat_i : in std_logic_vector(15 downto 0); + icap_dat_o : out std_logic_vector(15 downto 0); + icap_busy_i : in std_logic; + icap_ce_n_o : out std_logic; + icap_wr_n_o : out std_logic + ); +end entity multiboot_fsm; + + +architecture behav of multiboot_fsm is + + --============================================================================ + -- Type declarations + --============================================================================ + type t_state is + ( + -- idle state + IDLE, + -- SPI states + SPI_XFER1, + SPI_XFER2, + -- Config logic synchronization states + DUMMY_1, + DUMMY_2, + SYNC_H, + SYNC_L, + SYNC_NOOP, + -- IPROG states + GEN_1, + MBA_L, + GEN_2, + MBA_H, + GEN_3, + GBA_L, + GEN_4, + GBA_H, + IPROG_CMD, + IPROG, + -- RDCFGREG read states + RDCFGREG_CMD, + RDCFGREG_NOOP_1, + RDCFGREG_NOOP_2, + RDCFGREG_NOOP_3, + RDCFGREG_NOOP_4, + RDCFGREG_SETRD_1, + RDCFGREG_SETRD_2, + RDCFGREG_SETRD_3, + RDCFGREG, + RDCFGREG_SETWR_1, + RDCFGREG_SETWR_2, + RDCFGREG_SETWR_3, + DESYNC_CMD, + DESYNC, + -- NOOPs after RDCFGREG and IPROG sequences + FINAL_NOOP_1, + FINAL_NOOP_2, + PREPARE_IDLE + ); + + --============================================================================ + -- Signal declarations + --============================================================================ + signal state : t_state; + + signal fsm_cmd : std_logic_vector(2 downto 0); + signal fsm_cmd_reg : std_logic_vector(2 downto 0); + + signal fl_bcnt : unsigned(1 downto 0); + + signal fl_sreg : std_logic_vector(31 downto 0); + + signal first : std_logic; + + signal spi_data_int : std_logic_vector(23 downto 0); + signal spi_cnt : unsigned(1 downto 0); + +--============================================================================== +-- architecture begin +--============================================================================== +begin + + --============================================================================ + -- FSM logic + --============================================================================ + -- Form state machine command vector from inputs + fsm_cmd <= reg_far_xfer_i & + reg_iprog_i & + reg_rdcfgreg_i; + + -- Assign SPI outputs + spi_cs_o <= reg_far_cs_i; + spi_data_o <= spi_data_int(7 downto 0); + + -- The state machine process + p_fsm : process(clk_i) + variable v_idx : integer := 0; + begin + if rising_edge(clk_i) then + if (rst_n_i = '0') then + state <= IDLE; + fsm_cmd_reg <= (others => '0'); + icap_dat_o <= (others => '0'); + icap_ce_n_o <= '1'; + icap_wr_n_o <= '1'; + reg_cfgreg_img_o <= (others => '0'); + reg_cfgreg_valid_o <= '0'; + reg_far_ready_o <= '1'; + reg_far_data_o <= (others => '0'); + spi_data_int <= (others => '0'); + spi_cnt <= "00"; + spi_xfer_o <= '0'; + + else + + case state is + + --==================================================================== + -- IDLE: wait for a register bit to be set + --==================================================================== + when IDLE => + icap_ce_n_o <= '1'; + icap_wr_n_o <= '1'; + fsm_cmd_reg <= fsm_cmd; + case fsm_cmd is + when "010" | "001" => + state <= DUMMY_1; + when "100" => + spi_cnt <= "00"; + spi_data_int <= reg_far_data_i; + reg_far_data_o <= (others => '0'); + reg_far_ready_o <= '0'; + state <= SPI_XFER1; + when others => + state <= IDLE; + end case; + + --==================================================================== + -- Flash read sequence + --==================================================================== + -- set the transfer bit to the SPI master + when SPI_XFER1 => + spi_xfer_o <= '1'; + state <= SPI_XFER2; + + -- wait for SPI master to be ready and shift out new bytes, or go back + -- to idle if we've finished the number of bytes we have to send + when SPI_XFER2 => + spi_xfer_o <= '0'; + if (spi_ready_i = '1') then + -- prepare next byte to be sent + spi_cnt <= spi_cnt + 1; + spi_data_int <= x"00" & spi_data_int(23 downto 8); + state <= SPI_XFER1; + -- or if we've sent NBYTES, go back to IDLE + if (spi_cnt = unsigned(reg_far_nbytes_i)) then + reg_far_ready_o <= '1'; + state <= IDLE; + end if; + -- finally, place the received byte in the appropriate position + -- of the FAR data field + v_idx := to_integer(unsigned(spi_cnt)); + reg_far_data_o((1+v_idx)*8 - 1 downto v_idx*8) <= spi_data_i; + end if; + + --==================================================================== + -- Synchronization sequence + four NOOPs + -- as per Table 6-1, p. 113 [1], steps 1-10 + --==================================================================== + -- two dummy words + when DUMMY_1 => + icap_dat_o <= x"ffff"; + icap_ce_n_o <= '0'; + icap_wr_n_o <= '0'; + state <= DUMMY_2; + + when DUMMY_2 => + icap_dat_o <= x"ffff"; + icap_ce_n_o <= '0'; + icap_wr_n_o <= '0'; + state <= SYNC_H; + + -- now the two sync words + when SYNC_H => + icap_dat_o <= x"aa99"; + icap_ce_n_o <= '0'; + icap_wr_n_o <= '0'; + state <= SYNC_L; + + when SYNC_L => + icap_dat_o <= x"5566"; + icap_ce_n_o <= '0'; + icap_wr_n_o <= '0'; + state <= SYNC_NOOP; + + -- and the NOOP after the sync words, after which we go to IPROG or + -- RDCFGREG read, depending on what command we got at the beginning + when SYNC_NOOP => + icap_dat_o <= x"2000"; + icap_ce_n_o <= '0'; + icap_wr_n_o <= '0'; + case fsm_cmd_reg is + when "010" => + state <= GEN_1; + when "001" => + state <= RDCFGREG_CMD; + when others => + state <= IDLE; + end case; + + --==================================================================== + -- IPROG sequence + -- as per Table 7-1, p. 130 [1], starting from step 4 onward + --==================================================================== + when GEN_1 => + icap_dat_o <= x"3261"; + icap_ce_n_o <= '0'; + icap_wr_n_o <= '0'; + state <= MBA_L; + + when MBA_L => + icap_dat_o <= reg_mbbar_i(15 downto 0); + icap_ce_n_o <= '0'; + icap_wr_n_o <= '0'; + state <= GEN_2; + + when GEN_2 => + icap_dat_o <= x"3281"; + icap_ce_n_o <= '0'; + icap_wr_n_o <= '0'; + state <= MBA_H; + + when MBA_H => + icap_dat_o <= reg_mbbar_i(31 downto 16); + icap_ce_n_o <= '0'; + icap_wr_n_o <= '0'; + state <= GEN_3; + + when GEN_3 => + icap_dat_o <= x"32a1"; + icap_ce_n_o <= '0'; + icap_wr_n_o <= '0'; + state <= GBA_L; + + when GBA_L => + icap_dat_o <= reg_gbbar_i(15 downto 0); + icap_ce_n_o <= '0'; + icap_wr_n_o <= '0'; + state <= GEN_4; + + when GEN_4 => + icap_dat_o <= x"32c1"; + icap_ce_n_o <= '0'; + icap_wr_n_o <= '0'; + state <= GBA_H; + + when GBA_H => + icap_dat_o <= reg_gbbar_i(31 downto 16); + icap_ce_n_o <= '0'; + icap_wr_n_o <= '0'; + state <= IPROG_CMD; + + when IPROG_CMD => + icap_dat_o <= x"30a1"; + icap_ce_n_o <= '0'; + icap_wr_n_o <= '0'; + state <= IPROG; + + when IPROG => + icap_dat_o <= x"000e"; + icap_ce_n_o <= '0'; + icap_wr_n_o <= '0'; + state <= FINAL_NOOP_1; + + --==================================================================== + -- RDCFGREG read sequence + -- as per Table 6-1, p.113 [1], starting from step 6 + --==================================================================== + -- write type1 packet header to read CFGREGADR register + -- (packet headers can be found on page 93 of [1]) + when RDCFGREG_CMD => + icap_ce_n_o <= '0'; + icap_wr_n_o <= '0'; + icap_dat_o <= "001" & "01" & reg_cfgregadr_i & "00001"; + state <= RDCFGREG_NOOP_1; + + -- then four noops + when RDCFGREG_NOOP_1 => + icap_dat_o <= x"2000"; + icap_ce_n_o <= '0'; + icap_wr_n_o <= '0'; + state <= RDCFGREG_NOOP_2; + + when RDCFGREG_NOOP_2 => + icap_dat_o <= x"2000"; + icap_ce_n_o <= '0'; + icap_wr_n_o <= '0'; + state <= RDCFGREG_NOOP_3; + + when RDCFGREG_NOOP_3 => + icap_dat_o <= x"2000"; + icap_ce_n_o <= '0'; + icap_wr_n_o <= '0'; + state <= RDCFGREG_NOOP_4; + + when RDCFGREG_NOOP_4 => + icap_dat_o <= x"2000"; + icap_ce_n_o <= '0'; + icap_wr_n_o <= '0'; + state <= RDCFGREG_SETRD_1; + + -- smooth transition of the ICAP write input from write to read + -- (keep CS high while changing WRITE) + when RDCFGREG_SETRD_1 => + icap_ce_n_o <= '1'; + icap_wr_n_o <= '0'; + state <= RDCFGREG_SETRD_2; + + when RDCFGREG_SETRD_2 => + icap_ce_n_o <= '1'; + icap_wr_n_o <= '1'; + state <= RDCFGREG_SETRD_3; + + when RDCFGREG_SETRD_3 => + icap_ce_n_o <= '0'; + icap_wr_n_o <= '1'; + state <= RDCFGREG; + + -- this is where we actually read the value of RDCFGREG; + -- data retrieved by ICAP interface is valid when busy is low + when RDCFGREG => + icap_ce_n_o <= '0'; + icap_wr_n_o <= '1'; + if (icap_busy_i = '0') then + reg_cfgreg_img_o <= icap_dat_i; + reg_cfgreg_valid_o <= '1'; + state <= RDCFGREG_SETWR_1; + end if; + + -- smooth transition of the ICAP write input from read to write + -- (keep CS high while changing WRITE) + when RDCFGREG_SETWR_1 => + icap_ce_n_o <= '1'; + icap_wr_n_o <= '1'; + state <= RDCFGREG_SETWR_2; + + when RDCFGREG_SETWR_2 => + icap_ce_n_o <= '1'; + icap_wr_n_o <= '0'; + state <= RDCFGREG_SETWR_3; + + when RDCFGREG_SETWR_3 => + icap_ce_n_o <= '0'; + icap_wr_n_o <= '0'; + if (icap_busy_i = '0') then + state <= DESYNC_CMD; + end if; + + -- write 1 word to CMD register + when DESYNC_CMD => + icap_ce_n_o <= '0'; + icap_wr_n_o <= '0'; + icap_dat_o <= x"30a1"; + state <= DESYNC; + + -- write the DESYNC command + when DESYNC => + icap_ce_n_o <= '0'; + icap_wr_n_o <= '0'; + icap_dat_o <= x"000d"; + state <= FINAL_NOOP_1; + + --==================================================================== + -- Two NOOPs at end of all prog sequences + --==================================================================== + when FINAL_NOOP_1 => + icap_ce_n_o <= '0'; + icap_wr_n_o <= '0'; + icap_dat_o <= x"2000"; + state <= FINAL_NOOP_2; + + when FINAL_NOOP_2 => + icap_ce_n_o <= '0'; + icap_wr_n_o <= '0'; + icap_dat_o <= x"2000"; + state <= PREPARE_IDLE; + + --==================================================================== + -- Prepare transition to CE='1', WR='1' in IDLE state + --==================================================================== + when PREPARE_IDLE => + icap_ce_n_o <= '1'; + icap_wr_n_o <= '0'; + state <= IDLE; + + --==================================================================== + -- Go to IDLE in case of state error + --==================================================================== + when others => + state <= IDLE; + + end case; + end if; + end if; + end process p_fsm; + +end architecture behav; +--============================================================================== +-- architecture end +--============================================================================== diff --git a/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd b/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd new file mode 100644 index 0000000000000000000000000000000000000000..c2fc1f85e634fe51573785cd5f2e26d3dc7d48c0 --- /dev/null +++ b/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd @@ -0,0 +1,281 @@ +--============================================================================== +-- CERN (BE-CO-HT) +-- Wishbone registers for xil_multiboot design +--============================================================================== +-- +-- author: auto-generated by wbgen2 from conv_regs.wb and modified by +-- Theodor Stana (t.stana@cern.ch) +-- +-- date of creation: 2013-08-19 +-- +-- version: 1.0 +-- +-- description: +-- Implements the registers and Wishbone interface for the MultiBoot design. +-- +--============================================================================== +-- GNU LESSER GENERAL PUBLIC LICENSE +--============================================================================== +-- This source file is free software; you can redistribute it and/or modify it +-- under the terms of the GNU Lesser General Public License as published by the +-- Free Software Foundation; either version 2.1 of the License, or (at your +-- option) any later version. This source is distributed in the hope that it +-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty +-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +-- See the GNU Lesser General Public License for more details. You should have +-- received a copy of the GNU Lesser General Public License along with this +-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html +--============================================================================== +-- last changes: +-- 2013-08-19 Theodor Stana t.stana@cern.ch File created +--============================================================================== +-- TODO: - +--============================================================================== + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity multiboot_regs is + port ( + -- Clock and reset inputs + rst_n_i : in std_logic; + clk_sys_i : in std_logic; + + -- Wishbone ports + wb_adr_i : in std_logic_vector(2 downto 0); + wb_dat_i : in std_logic_vector(31 downto 0); + wb_dat_o : out std_logic_vector(31 downto 0); + wb_cyc_i : in std_logic; + wb_sel_i : in std_logic_vector(3 downto 0); + wb_stb_i : in std_logic; + wb_we_i : in std_logic; + wb_ack_o : out std_logic; + wb_stall_o : out std_logic; + + -- Fields of control register + multiboot_cr_rdcfgreg_o : out std_logic; + multiboot_cr_cfgregadr_o : out std_logic_vector(5 downto 0); + multiboot_cr_iprog_o : out std_logic; + + -- Fields of status register + multiboot_sr_cfgreg_img_i : in std_logic_vector(15 downto 0); + multiboot_sr_valid_i : in std_logic; + + -- Fields of bitstream address registers + multiboot_gbbar_o : out std_logic_vector(31 downto 0); + multiboot_mbbar_o : out std_logic_vector(31 downto 0); + + -- Fields of FAR register + multiboot_far_data_i : in std_logic_vector(23 downto 0); + multiboot_far_data_o : out std_logic_vector(23 downto 0); + multiboot_far_nbytes_o : out std_logic_vector(1 downto 0); + multiboot_far_xfer_o : out std_logic; + multiboot_far_cs_o : out std_logic; + multiboot_far_ready_i : in std_logic + ); +end multiboot_regs; + +architecture behav of multiboot_regs is + +signal multiboot_cr_rdcfgreg_int : std_logic; +signal multiboot_cr_cfgregadr_int : std_logic_vector(5 downto 0); +signal multiboot_cr_iprog_int : std_logic; +signal multiboot_cr_iprog_unl_int : std_logic; +signal multiboot_cr_flr_int : std_logic; +signal multiboot_cr_flw_int : std_logic; +signal multiboot_sr_cfgreg_img_int : std_logic_vector(15 downto 0); +signal multiboot_sr_valid_int : std_logic; +signal multiboot_sr_flrrdy_int : std_logic; +signal multiboot_sr_flwrdy_int : std_logic; +signal multiboot_gbbar_int : std_logic_vector(31 downto 0); +signal multiboot_mbbar_int : std_logic_vector(31 downto 0); +signal multiboot_flrdr_int : std_logic_vector(31 downto 0); +signal multiboot_flwdr_int : std_logic_vector(31 downto 0); +signal multiboot_far_data_load_int : std_logic; +signal multiboot_far_data_int : std_logic_vector(23 downto 0); +signal multiboot_far_nbytes_int : std_logic_vector(1 downto 0); +signal multiboot_far_xfer_int : std_logic; +signal multiboot_far_cs_int : std_logic; +signal multiboot_far_ready_int : std_logic; +signal ack_sreg : std_logic_vector(1 downto 0); +signal rddata_reg : std_logic_vector(31 downto 0); +signal wrdata_reg : std_logic_vector(31 downto 0); +signal rwaddr_reg : std_logic_vector(2 downto 0); +signal ack_in_progress : std_logic; + +begin + +-- Some internal signals assignments. + wrdata_reg <= wb_dat_i; + rwaddr_reg <= wb_adr_i; + + multiboot_sr_cfgreg_img_int <= multiboot_sr_cfgreg_img_i; + multiboot_sr_valid_int <= multiboot_sr_valid_i; + + multiboot_far_ready_int <= multiboot_far_ready_i; + +-- Main register bank access process. + process (clk_sys_i, rst_n_i) + begin + if (rst_n_i = '0') then + ack_sreg <= (others => '0'); + ack_in_progress <= '0'; + rddata_reg <= (others => '0'); + multiboot_cr_rdcfgreg_int <= '0'; + multiboot_cr_cfgregadr_int <= (others => '0'); + multiboot_cr_iprog_int <= '0'; + multiboot_cr_iprog_unl_int <= '0'; + multiboot_gbbar_int <= (others => '0'); + multiboot_mbbar_int <= (others => '0'); + multiboot_far_nbytes_int <= "00"; + multiboot_far_data_int <= (others => '0'); + multiboot_far_cs_int <= '0'; + multiboot_far_xfer_int <= '0'; + elsif rising_edge(clk_sys_i) then +-- advance the ACK generator shift register + ack_sreg(0) <= ack_sreg(1); + ack_sreg(1) <= '0'; + if (ack_in_progress = '1') then + multiboot_cr_rdcfgreg_int <= '0'; + multiboot_far_xfer_int <= '0'; + if (ack_sreg(0) = '1') then + ack_in_progress <= '0'; + else + end if; + else + if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then + case rwaddr_reg is + when "000" => + if (wb_we_i = '1') then + multiboot_cr_cfgregadr_int <= wrdata_reg(5 downto 0); + multiboot_cr_rdcfgreg_int <= wrdata_reg(6); + multiboot_cr_iprog_unl_int <= wrdata_reg(16); + if (multiboot_cr_iprog_unl_int = '1') then + multiboot_cr_iprog_int <= wrdata_reg(17); + end if; + end if; + rddata_reg(5 downto 0) <= multiboot_cr_cfgregadr_int; + rddata_reg(6) <= multiboot_cr_rdcfgreg_int; + rddata_reg(7) <= 'X'; + rddata_reg(8) <= 'X'; + rddata_reg(9) <= 'X'; + rddata_reg(10) <= 'X'; + rddata_reg(11) <= 'X'; + rddata_reg(12) <= 'X'; + rddata_reg(13) <= 'X'; + rddata_reg(14) <= 'X'; + rddata_reg(15) <= 'X'; + rddata_reg(16) <= multiboot_cr_iprog_unl_int; + rddata_reg(17) <= multiboot_cr_iprog_int; + rddata_reg(18) <= 'X'; + rddata_reg(19) <= 'X'; + rddata_reg(20) <= 'X'; + rddata_reg(21) <= 'X'; + rddata_reg(22) <= 'X'; + rddata_reg(23) <= 'X'; + rddata_reg(24) <= 'X'; + rddata_reg(25) <= 'X'; + rddata_reg(26) <= 'X'; + rddata_reg(27) <= 'X'; + rddata_reg(28) <= 'X'; + rddata_reg(29) <= 'X'; + rddata_reg(30) <= 'X'; + rddata_reg(31) <= 'X'; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "001" => + if (wb_we_i = '1') then + end if; + rddata_reg(15 downto 0) <= multiboot_sr_cfgreg_img_int; + rddata_reg(16) <= multiboot_sr_valid_int; + rddata_reg(17) <= 'X'; + rddata_reg(18) <= 'X'; + rddata_reg(19) <= 'X'; + rddata_reg(20) <= 'X'; + rddata_reg(21) <= 'X'; + rddata_reg(22) <= 'X'; + rddata_reg(23) <= 'X'; + rddata_reg(24) <= 'X'; + rddata_reg(25) <= 'X'; + rddata_reg(26) <= 'X'; + rddata_reg(27) <= 'X'; + rddata_reg(28) <= 'X'; + rddata_reg(29) <= 'X'; + rddata_reg(30) <= 'X'; + rddata_reg(31) <= 'X'; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "010" => + if (wb_we_i = '1') then + multiboot_gbbar_int <= wrdata_reg; + end if; + rddata_reg <= multiboot_gbbar_int; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "011" => + if (wb_we_i = '1') then + multiboot_mbbar_int <= wrdata_reg; + end if; + rddata_reg <= multiboot_mbbar_int; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when "100" => + if (wb_we_i = '1') then + multiboot_far_data_int <= wrdata_reg(23 downto 0); + multiboot_far_nbytes_int <= wrdata_reg(25 downto 24); + multiboot_far_xfer_int <= wrdata_reg(26); + multiboot_far_cs_int <= wrdata_reg(27); + end if; + rddata_reg(23 downto 0) <= multiboot_far_data_i; + rddata_reg(25 downto 24) <= multiboot_far_nbytes_int; + rddata_reg(26) <= multiboot_far_xfer_int; + rddata_reg(27) <= multiboot_far_cs_int; + rddata_reg(28) <= multiboot_far_ready_int; + rddata_reg(29) <= 'X'; + rddata_reg(30) <= 'X'; + rddata_reg(31) <= 'X'; + ack_sreg(0) <= '1'; + ack_in_progress <= '1'; + when others => +-- prevent the slave from hanging the bus on invalid address + ack_in_progress <= '1'; + ack_sreg(0) <= '1'; + end case; + end if; + end if; + end if; + end process; + + +-- Drive the data output bus + wb_dat_o <= rddata_reg; + +-- Drive the stall line + wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i); + +-- Configuration register address + multiboot_cr_cfgregadr_o <= multiboot_cr_cfgregadr_int; + +-- Read configuration register + multiboot_cr_rdcfgreg_o <= multiboot_cr_rdcfgreg_int; + +-- IPROG + multiboot_cr_iprog_o <= multiboot_cr_iprog_int; + +-- GBBAR + multiboot_gbbar_o <= multiboot_gbbar_int; + +-- MBBAR + multiboot_mbbar_o <= multiboot_mbbar_int; + +-- FAR outputs + multiboot_far_data_o <= multiboot_far_data_int; --wrdata_reg(23 downto 0); + multiboot_far_nbytes_o <= multiboot_far_nbytes_int; + multiboot_far_xfer_o <= multiboot_far_xfer_int; + multiboot_far_cs_o <= multiboot_far_cs_int; + + -- ACK signal generation. Just pass the LSB of ACK counter. + wb_ack_o <= ack_sreg(0); + +end behav; diff --git a/platform/xilinx/wb_xil_multiboot/spi_master.vhd b/platform/xilinx/wb_xil_multiboot/spi_master.vhd new file mode 100644 index 0000000000000000000000000000000000000000..59c31548ff3ef2f161fe6d628b90561ad3e97128 --- /dev/null +++ b/platform/xilinx/wb_xil_multiboot/spi_master.vhd @@ -0,0 +1,206 @@ +----------------------------------------------------------------------------- +-- Title : SPI Bus Master +-- Project : Simple VME64x FMC Carrier (SVEC) +------------------------------------------------------------------------------- +-- File : spi_master.vhd +-- Author : Tomasz Wlostowski +-- Company : CERN +-- Created : 2011-08-24 +-- Last update: 2013-01-25 +-- Platform : FPGA-generic +-- Standard : VHDL'93 +------------------------------------------------------------------------------- +-- Description: Just a simple SPI master (bus-less). +------------------------------------------------------------------------------- +-- +-- Copyright (c) 2011-2013 CERN / BE-CO-HT +-- +-- This source file is free software; you can redistribute it +-- and/or modify it under the terms of the GNU Lesser General +-- Public License as published by the Free Software Foundation; +-- either version 2.1 of the License, or (at your option) any +-- later version. +-- +-- This source is distributed in the hope that it will be +-- useful, but WITHOUT ANY WARRANTY; without even the implied +-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +-- PURPOSE. See the GNU Lesser General Public License for more +-- details. +-- +-- You should have received a copy of the GNU Lesser General +-- Public License along with this source; if not, download it +-- from http://www.gnu.org/licenses/lgpl-2.1.html +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity spi_master is + generic( + -- clock division ratio (SCLK = clk_sys_i / (2 ** g_div_ratio_log2). + g_div_ratio_log2 : integer := 2; + -- number of data bits per transfer + g_num_data_bits : integer := 2); + port ( + clk_sys_i : in std_logic; + rst_n_i : in std_logic; + + -- state of the Chip select line (1 = CS active). External control + -- allows for multi-transfer commands (SPI master itself does not + -- control the state of spi_cs_n_o) + cs_i : in std_logic; + + -- 1: start next transfer (using CPOL, DATA and SEL from the inputs below) + start_i : in std_logic; + + -- Clock polarity: 1: slave clocks in the data on rising SCLK edge, 0: ... + -- on falling SCLK edge + cpol_i : in std_logic; + + -- TX Data input + data_i : in std_logic_vector(g_num_data_bits - 1 downto 0); + + -- 1: data_o contains the result of last read operation. Core is ready to initiate + -- another transfer. + ready_o : out std_logic; + + -- data read from selected slave, valid when ready_o == 1. + data_o : out std_logic_vector(g_num_data_bits - 1 downto 0); + + -- these are obvious + spi_cs_n_o : out std_logic; + spi_sclk_o : out std_logic; + spi_mosi_o : out std_logic; + spi_miso_i : in std_logic + ); + +end spi_master; + +architecture behavioral of spi_master is + + signal divider : unsigned(11 downto 0); + signal tick : std_logic; + + signal sreg : std_logic_vector(g_num_data_bits-1 downto 0); + signal rx_sreg : std_logic_vector(g_num_data_bits-1 downto 0); + + type t_state is (IDLE, TX_CS, TX_DAT1, TX_DAT2, TX_SCK1, TX_SCK2, TX_CS2, TX_GAP); + signal state : t_state; + signal sclk : std_logic; + + signal counter : unsigned(4 downto 0); + +begin -- rtl + + -- Simple clock divder. Produces a 'tick' signal which defines the timing for + -- the main state machine transitions. + p_divide_spi_clock: process(clk_sys_i) + begin + if rising_edge(clk_sys_i) then + if rst_n_i = '0' then + divider <= (others => '0'); + else + if(start_i = '1' or tick = '1') then + divider <= (others => '0'); + else + divider <= divider + 1; + end if; + end if; + end if; + end process; + + tick <= divider(g_div_ratio_log2); + + -- Main state machine. Executes SPI transfers + p_main_fsm: process(clk_sys_i) + begin + if rising_edge(clk_sys_i) then + if rst_n_i = '0' then + state <= IDLE; + sclk <= '0'; + sreg <= (others => '0'); + rx_sreg <= (others => '0'); + spi_mosi_o <= '0'; + data_o <= (others => '0'); + counter <= (others => '0'); + else + case state is + -- Waits for start of transfer command + when IDLE => + sclk <= '0'; + counter <= (others => '0'); + if(start_i = '1') then + sreg <= data_i; + state <= TX_CS; + spi_mosi_o <= data_i(sreg'high); + end if; + + -- Generates a gap between the externally asserted Chip Select and + -- the beginning of data transfer + when TX_CS => + if tick = '1' then + state <= TX_DAT1; + end if; + + -- Outputs subsequent bits to MOSI line. + when TX_DAT1 => + if(tick = '1') then + spi_mosi_o <= sreg(sreg'high); + sreg <= sreg(sreg'high-1 downto 0) & '0'; + state <= TX_SCK1; + end if; + + -- Flips the SCLK (active edge) + when TX_SCK1 => + if(tick = '1') then + sclk <= not sclk; + counter <= counter + 1; + state <= TX_DAT2; + end if; + + -- Shifts in bits read from the slave + when TX_DAT2 => + + if(tick = '1') then + rx_sreg <= rx_sreg(rx_sreg'high-1 downto 0) & spi_miso_i; + state <= TX_SCK2; + end if; + + -- Flips the SCLK (inactive edge). Checks if all bits have been + -- transferred. + when TX_SCK2 => + if(tick = '1') then + sclk <= not sclk; + if(counter = g_num_data_bits) then + state <= TX_CS2; + else + state <= TX_DAT1; + end if; + end if; + + -- Generates a gap for de-assertoin of CS line + when TX_CS2 => + if(tick = '1') then + state <= TX_GAP; + data_o <= rx_sreg; + end if; + + when TX_GAP => + if (tick = '1') then + state <= IDLE; + end if; + end case; + end if; + end if; + end process; + + ready_o <= '1' when (state = IDLE and start_i = '0') else '0'; + + -- SCLK polarity control + spi_sclk_o <= sclk xor cpol_i; + spi_cs_n_o <= not cs_i; + +end behavioral; + diff --git a/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd b/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd new file mode 100644 index 0000000000000000000000000000000000000000..aec6138873ed9713add791bcb5d30ee4f05aca2f --- /dev/null +++ b/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd @@ -0,0 +1,394 @@ +--============================================================================== +-- CERN (BE-CO-HT) +-- Xilinx MultiBoot core top-level file +--============================================================================== +-- +-- author: Theodor Stana (t.stana@cern.ch) +-- +-- date of creation: 2013-08-19 +-- +-- version: 1.0 +-- +-- description: +-- +-- dependencies: +-- +-- references: +-- +--============================================================================== +-- GNU LESSER GENERAL PUBLIC LICENSE +--============================================================================== +-- This source file is free software; you can redistribute it and/or modify it +-- under the terms of the GNU Lesser General Public License as published by the +-- Free Software Foundation; either version 2.1 of the License, or (at your +-- option) any later version. This source is distributed in the hope that it +-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty +-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +-- See the GNU Lesser General Public License for more details. You should have +-- received a copy of the GNU Lesser General Public License along with this +-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html +--============================================================================== +-- last changes: +-- 2013-08-19 Theodor Stana t.stana@cern.ch File created +--============================================================================== +-- TODO: - +--============================================================================== + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library unisim; +use unisim.vcomponents.all; + +use work.wishbone_pkg.all; + +entity wb_xil_multiboot is + port + ( + -- Clock and reset input ports + clk_i : in std_logic; + rst_n_i : in std_logic; + + -- Wishbone ports + wbs_i : in t_wishbone_slave_in; + wbs_o : out t_wishbone_slave_out; + + -- SPI ports + spi_cs_n_o : out std_logic; + spi_sclk_o : out std_logic; + spi_mosi_o : out std_logic; + spi_miso_i : in std_logic + ); +end entity wb_xil_multiboot; + + +architecture struct of wb_xil_multiboot is + + --============================================================================ + -- Component declarations + --============================================================================ + -- Register component + component multiboot_regs is + port ( + -- Clock and reset inputs + rst_n_i : in std_logic; + clk_sys_i : in std_logic; + + -- Wishbone ports + wb_adr_i : in std_logic_vector(2 downto 0); + wb_dat_i : in std_logic_vector(31 downto 0); + wb_dat_o : out std_logic_vector(31 downto 0); + wb_cyc_i : in std_logic; + wb_sel_i : in std_logic_vector(3 downto 0); + wb_stb_i : in std_logic; + wb_we_i : in std_logic; + wb_ack_o : out std_logic; + wb_stall_o : out std_logic; + + -- Fields of control register + multiboot_cr_rdcfgreg_o : out std_logic; + multiboot_cr_cfgregadr_o : out std_logic_vector(5 downto 0); + multiboot_cr_iprog_o : out std_logic; + + -- Fields of status register + multiboot_sr_cfgreg_img_i : in std_logic_vector(15 downto 0); + multiboot_sr_valid_i : in std_logic; + + -- Fields of bitstream address registers + multiboot_gbbar_o : out std_logic_vector(31 downto 0); + multiboot_mbbar_o : out std_logic_vector(31 downto 0); + + -- Fields of FAR register + multiboot_far_data_i : in std_logic_vector(23 downto 0); + multiboot_far_data_o : out std_logic_vector(23 downto 0); + multiboot_far_nbytes_o : out std_logic_vector(1 downto 0); + multiboot_far_xfer_o : out std_logic; + multiboot_far_cs_o : out std_logic; + multiboot_far_ready_i : in std_logic + ); + end component multiboot_regs; + + -- FSM component + component multiboot_fsm is + port + ( + -- Clock and reset inputs + clk_i : in std_logic; + rst_n_i : in std_logic; + + -- Control register inputs + reg_rdcfgreg_i : in std_logic; + reg_cfgregadr_i : in std_logic_vector(5 downto 0); + reg_iprog_i : in std_logic; + + -- Multiboot and golden bitstream start addresses + reg_gbbar_i : in std_logic_vector(31 downto 0); + reg_mbbar_i : in std_logic_vector(31 downto 0); + + -- Outputs to status register + reg_cfgreg_img_o : out std_logic_vector(15 downto 0); + reg_cfgreg_valid_o : out std_logic; + + -- Flash access register signals + reg_far_data_i : in std_logic_vector(23 downto 0); + reg_far_data_o : out std_logic_vector(23 downto 0); + reg_far_nbytes_i : in std_logic_vector(1 downto 0); + reg_far_xfer_i : in std_logic; + reg_far_cs_i : in std_logic; + reg_far_ready_o : out std_logic; + + -- SPI master signals + spi_xfer_o : out std_logic; + spi_cs_o : out std_logic; + spi_data_i : in std_logic_vector(7 downto 0); + spi_data_o : out std_logic_vector(7 downto 0); + spi_ready_i : in std_logic; + + -- Ports for the external ICAP component + icap_dat_i : in std_logic_vector(15 downto 0); + icap_dat_o : out std_logic_vector(15 downto 0); + icap_busy_i : in std_logic; + icap_ce_n_o : out std_logic; + icap_wr_n_o : out std_logic + ); + end component multiboot_fsm; + + -- SPI master + component spi_master is + generic( + -- clock division ratio (SCLK = clk_sys_i / (2 ** g_div_ratio_log2). + g_div_ratio_log2 : integer := 2; + -- number of data bits per transfer + g_num_data_bits : integer := 2); + port ( + clk_sys_i : in std_logic; + rst_n_i : in std_logic; + + -- state of the Chip select line (1 = CS active). External control + -- allows for multi-transfer commands (SPI master itself does not + -- control the state of spi_cs_n_o) + cs_i : in std_logic; + + -- 1: start next transfer (using CPOL, DATA and SEL from the inputs below) + start_i : in std_logic; + + -- Clock polarity: 1: slave clocks in the data on rising SCLK edge, 0: ... + -- on falling SCLK edge + cpol_i : in std_logic; + + -- TX Data input + data_i : in std_logic_vector(g_num_data_bits - 1 downto 0); + + -- 1: data_o contains the result of last read operation. Core is ready to initiate + -- another transfer. + ready_o : out std_logic; + + -- data read from selected slave, valid when ready_o == 1. + data_o : out std_logic_vector(g_num_data_bits - 1 downto 0); + + -- these are obvious + spi_cs_n_o : out std_logic; + spi_sclk_o : out std_logic; + spi_mosi_o : out std_logic; + spi_miso_i : in std_logic + ); + end component spi_master; + + --============================================================================ + -- Signal declarations + --============================================================================ + -- Control and status register signals + signal rdcfgreg : std_logic; + signal cfgregadr : std_logic_vector(5 downto 0); + signal iprog : std_logic; + signal cfgreg_img : std_logic_vector(15 downto 0); + signal sr_valid : std_logic; + signal gbbar, mbbar : std_logic_vector(31 downto 0); + + -- FSM signals + signal fsm_icap_din : std_logic_vector(15 downto 0); + signal fsm_icap_dout : std_logic_vector(15 downto 0); + + -- Flash controller signals + signal far_data_out : std_logic_vector(23 downto 0); + signal far_data_in : std_logic_vector(23 downto 0); + signal far_nbytes : std_logic_vector(1 downto 0); + signal far_xfer : std_logic; + signal far_cs : std_logic; + signal far_ready : std_logic; + + -- SPI master signals + signal spi_data_in : std_logic_vector(7 downto 0); + signal spi_data_out : std_logic_vector(7 downto 0); + signal spi_xfer : std_logic; + signal spi_cs : std_logic; + signal spi_ready : std_logic; + + -- ICAP signals + signal icap_ce_n : std_logic; + signal icap_wr_n : std_logic; + signal icap_busy : std_logic; + signal icap_din : std_logic_vector(15 downto 0); + signal icap_dout : std_logic_vector(15 downto 0); + +--============================================================================== +-- architecture begin +--============================================================================== +begin + + --============================================================================ + -- Register component instantiation + --============================================================================ + cmp_regs : multiboot_regs + port map + ( + rst_n_i => rst_n_i, + clk_sys_i => clk_i, + + wb_adr_i => wbs_i.adr(4 downto 2), + wb_dat_i => wbs_i.dat, + wb_dat_o => wbs_o.dat, + wb_cyc_i => wbs_i.cyc, + wb_sel_i => wbs_i.sel, + wb_stb_i => wbs_i.stb, + wb_we_i => wbs_i.we, + wb_ack_o => wbs_o.ack, + wb_stall_o => wbs_o.stall, + + multiboot_cr_rdcfgreg_o => rdcfgreg, + multiboot_cr_cfgregadr_o => cfgregadr, + multiboot_cr_iprog_o => iprog, + + multiboot_sr_cfgreg_img_i => cfgreg_img, + multiboot_sr_valid_i => sr_valid, + + multiboot_gbbar_o => gbbar, + multiboot_mbbar_o => mbbar, + + multiboot_far_data_i => far_data_in, + multiboot_far_data_o => far_data_out, + multiboot_far_nbytes_o => far_nbytes, + multiboot_far_xfer_o => far_xfer, + multiboot_far_cs_o => far_cs, + multiboot_far_ready_i => far_ready + ); + + --============================================================================ + -- FSM component instantiation + --============================================================================ + cmp_fsm : multiboot_fsm + port map + ( + clk_i => clk_i, + rst_n_i => rst_n_i, + + reg_rdcfgreg_i => rdcfgreg, + reg_cfgregadr_i => cfgregadr, + reg_iprog_i => iprog, + + reg_gbbar_i => gbbar, + reg_mbbar_i => mbbar, + + reg_cfgreg_img_o => cfgreg_img, + reg_cfgreg_valid_o => sr_valid, + + reg_far_data_i => far_data_out, + reg_far_data_o => far_data_in, + reg_far_nbytes_i => far_nbytes, + reg_far_xfer_i => far_xfer, + reg_far_cs_i => far_cs, + reg_far_ready_o => far_ready, + + spi_xfer_o => spi_xfer, + spi_cs_o => spi_cs, + spi_data_i => spi_data_out, + spi_data_o => spi_data_in, + spi_ready_i => spi_ready, + + icap_dat_i => fsm_icap_din, + icap_dat_o => fsm_icap_dout, + icap_busy_i => icap_busy, + icap_ce_n_o => icap_ce_n, + icap_wr_n_o => icap_wr_n + ); + + --============================================================================ + -- Flash controller instantiation + --============================================================================ + cmp_spi_master : spi_master + generic map + ( + g_div_ratio_log2 => 0, + g_num_data_bits => 8 + ) + port map + ( + clk_sys_i => clk_i, + rst_n_i => rst_n_i, + cs_i => spi_cs, + start_i => spi_xfer, + cpol_i => '0', + data_i => spi_data_in, + data_o => spi_data_out, + ready_o => spi_ready, + spi_cs_n_o => spi_cs_n_o, + spi_sclk_o => spi_sclk_o, + spi_mosi_o => spi_mosi_o, + spi_miso_i => spi_miso_i + ); + + --============================================================================ + -- Xilinx ICAP logic + --============================================================================ + -- First, bit-flip the data to/from the FSM + icap_din( 0) <= fsm_icap_dout( 7); + icap_din( 1) <= fsm_icap_dout( 6); + icap_din( 2) <= fsm_icap_dout( 5); + icap_din( 3) <= fsm_icap_dout( 4); + icap_din( 4) <= fsm_icap_dout( 3); + icap_din( 5) <= fsm_icap_dout( 2); + icap_din( 6) <= fsm_icap_dout( 1); + icap_din( 7) <= fsm_icap_dout( 0); + icap_din( 8) <= fsm_icap_dout(15); + icap_din( 9) <= fsm_icap_dout(14); + icap_din(10) <= fsm_icap_dout(13); + icap_din(11) <= fsm_icap_dout(12); + icap_din(12) <= fsm_icap_dout(11); + icap_din(13) <= fsm_icap_dout(10); + icap_din(14) <= fsm_icap_dout( 9); + icap_din(15) <= fsm_icap_dout( 8); + + fsm_icap_din( 0) <= icap_dout( 7); + fsm_icap_din( 1) <= icap_dout( 6); + fsm_icap_din( 2) <= icap_dout( 5); + fsm_icap_din( 3) <= icap_dout( 4); + fsm_icap_din( 4) <= icap_dout( 3); + fsm_icap_din( 5) <= icap_dout( 2); + fsm_icap_din( 6) <= icap_dout( 1); + fsm_icap_din( 7) <= icap_dout( 0); + fsm_icap_din( 8) <= icap_dout(15); + fsm_icap_din( 9) <= icap_dout(14); + fsm_icap_din(10) <= icap_dout(13); + fsm_icap_din(11) <= icap_dout(12); + fsm_icap_din(12) <= icap_dout(11); + fsm_icap_din(13) <= icap_dout(10); + fsm_icap_din(14) <= icap_dout( 9); + fsm_icap_din(15) <= icap_dout( 8); + + -- and instantiate the ICAP component + cmp_icap : ICAP_SPARTAN6 + port map + ( + CLK => clk_i, + CE => icap_ce_n, + WRITE => icap_wr_n, + I => icap_din, + O => icap_dout, + BUSY => icap_busy + ); + +end architecture struct; +--============================================================================== +-- architecture end +--==============================================================================