From ac9ce6a0bf0e6cd1d0f916fc895f2c92b82a918d Mon Sep 17 00:00:00 2001
From: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
Date: Tue, 12 Jul 2011 16:25:16 +0200
Subject: [PATCH] wishbone_pkg: new components added to WB package and
manifests
---
modules/wishbone/Manifest.py | 4 +-
modules/wishbone/wishbone_pkg.vhd | 63 ++++++++++++++++++++++++++++---
2 files changed, 61 insertions(+), 6 deletions(-)
diff --git a/modules/wishbone/Manifest.py b/modules/wishbone/Manifest.py
index db6b407..0cbed6b 100644
--- a/modules/wishbone/Manifest.py
+++ b/modules/wishbone/Manifest.py
@@ -3,6 +3,8 @@ modules = { "local" :
[
# "wb_async_bridge",
"wb_onewire_master",
+ "wb_i2c_master",
+ "wb_bus_fanout",
"wb_conmax",
"wb_gpio_port",
"wb_simple_timer",
@@ -10,7 +12,7 @@ modules = { "local" :
"wb_vic",
"wb_spi",
"wb_virtual_uart",
- "wbgen2",
+ "wbgen2"
]};
files = ["wishbone_pkg.vhd"];
diff --git a/modules/wishbone/wishbone_pkg.vhd b/modules/wishbone/wishbone_pkg.vhd
index df774e0..6b0ff6a 100644
--- a/modules/wishbone/wishbone_pkg.vhd
+++ b/modules/wishbone/wishbone_pkg.vhd
@@ -46,9 +46,38 @@ package wishbone_pkg is
subtype t_wishbone_device_descriptor is std_logic_vector(255 downto 0);
+
+
+ type t_wishbone_master_out_array is array (natural range <>) of t_wishbone_master_out;
+ type t_wishbone_slave_out_array is array (natural range <>) of t_wishbone_slave_out;
+ type t_wishbone_master_in_array is array (natural range <>) of t_wishbone_master_in;
+ type t_wishbone_slave_in_array is array (natural range <>) of t_wishbone_slave_in;
+
+------------------------------------------------------------------------------
+-- Components declaration
+-------------------------------------------------------------------------------
+
+
+ component xwb_i2c_master
+ generic (
+ g_interface_mode : t_wishbone_interface_mode := CLASSIC);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ slave_i : in t_wishbone_slave_in;
+ slave_o : out t_wishbone_slave_out;
+ desc_o : out t_wishbone_device_descriptor;
+ scl_pad_i : in std_logic;
+ scl_pad_o : out std_logic;
+ scl_padoen_o : out std_logic;
+ sda_pad_i : in std_logic;
+ sda_pad_o : out std_logic;
+ sda_padoen_o : out std_logic);
+ end component;
+
component xwb_spi
generic (
- g_interface_mode : t_wishbone_interface_mode);
+ g_interface_mode : t_wishbone_interface_mode := CLASSIC);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
@@ -61,10 +90,34 @@ package wishbone_pkg is
pad_miso_i : in std_logic);
end component;
- type t_wishbone_master_out_array is array (natural range <>) of t_wishbone_master_out;
- type t_wishbone_slave_out_array is array (natural range <>) of t_wishbone_slave_out;
- type t_wishbone_master_in_array is array (natural range <>) of t_wishbone_master_in;
- type t_wishbone_slave_in_array is array (natural range <>) of t_wishbone_slave_in;
+ component xwb_onewire_master
+ generic (
+ g_interface_mode : t_wishbone_interface_mode := CLASSIC;
+ g_num_ports : integer := 1;
+ g_ow_btp_normal : string := "5.0";
+ g_ow_btp_overdrive : string := "1.0");
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ slave_i : in t_wishbone_slave_in;
+ slave_o : out t_wishbone_slave_out;
+ desc_o : out t_wishbone_device_descriptor;
+ owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
+ owr_en_o : out std_logic_vector(g_num_ports -1 downto 0);
+ owr_i : in std_logic_vector(g_num_ports -1 downto 0));
+ end component;
+ component xwb_bus_fanout
+ generic (
+ g_num_outputs : natural;
+ g_bits_per_slave : integer := 14);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ slave_i : in t_wishbone_slave_in;
+ slave_o : out t_wishbone_slave_out;
+ master_i : in t_wishbone_master_in_array(0 to g_num_outputs-1);
+ master_o : out t_wishbone_master_out_array(0 to g_num_outputs-1));
+ end component;
end wishbone_pkg;
--
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