diff --git a/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd b/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
index d8ec4794e3ea5144ee6b8f83a72cc5074a03f9f3..8e151a46b9fb341eae7c7aeb60c91ebd40a4f84c 100644
--- a/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
+++ b/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd
@@ -4,6 +4,9 @@ use ieee.std_logic_1164.all;
 use work.wishbone_pkg.all;
 
 entity xwb_i2c_master is
+  generic(
+    g_interface_mode         : t_wishbone_interface_mode := CLASSIC
+    );
   port (
     clk_sys_i : in std_logic;
     rst_n_i   : in std_logic;
@@ -51,6 +54,13 @@ architecture rtl of xwb_i2c_master is
   
 begin  -- rtl
 
+
+  gen_test_mode : if(g_interface_mode /= CLASSIC) generate
+
+    assert false report "xwb_i2c_master: this module can only work with CLASSIC wishbone interface" severity failure;
+
+  end generate gen_test_mode;
+  
   rst <= not rst_n_i;
 
   Wrapped_I2C : i2c_master_top