diff --git a/modules/wishbone/wb_crossbar/Manifest.py b/modules/wishbone/wb_crossbar/Manifest.py
index 968b4a3febe5da563566c1d54923b67e7c9ac187..f57dd47ee9f35330092796b65494a936180fb497 100644
--- a/modules/wishbone/wb_crossbar/Manifest.py
+++ b/modules/wishbone/wb_crossbar/Manifest.py
@@ -3,4 +3,5 @@ files = [
"xwb_crossbar.vhd",
"xwb_sdb_crossbar.vhd",
"xwb_register_link.vhd",
+ "wb_skidpad.vhd",
]
diff --git a/modules/wishbone/wbgenplus/wb_skidpad.vhd b/modules/wishbone/wb_crossbar/wb_skidpad.vhd
similarity index 100%
rename from modules/wishbone/wbgenplus/wb_skidpad.vhd
rename to modules/wishbone/wb_crossbar/wb_skidpad.vhd
diff --git a/modules/wishbone/wb_crossbar/xwb_register_link.vhd b/modules/wishbone/wb_crossbar/xwb_register_link.vhd
index 0ee697b535e3cff567a02b8b49d6bdd38096932e..34bd3d8b986497740cdfcb05fbd77ab4b7b9640e 100644
--- a/modules/wishbone/wb_crossbar/xwb_register_link.vhd
+++ b/modules/wishbone/wb_crossbar/xwb_register_link.vhd
@@ -6,22 +6,23 @@
-- Author : Wesley W. Terpstra
-- Company : GSI
-- Created : 2013-12-16
--- Last update: 2013-12-16
+-- Last update: 2016-04-12
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
--- Adds a register between two wishbone interfaces.
+-- Adds registers between two wishbone interfaces.
-- Useful to improve timing closure when placed between crossbars.
--- Be warned: it reduces the available bandwidth by a half.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2011 GSI / Wesley W. Terpstra
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
--- 2013-12-16 1.0 wterpstra V1
+-- 2013-12-16 1.0 wterpstra V1, half bandwidth
+-- 2016-04-12 2.0 mkreider reworked, now with full throughput
+
-------------------------------------------------------------------------------
@@ -42,34 +43,56 @@ end xwb_register_link;
architecture rtl of xwb_register_link is
- signal r_slave : t_wishbone_slave_out;
- signal r_master : t_wishbone_master_out;
+ signal s_push, s_pop : std_logic;
+ signal s_full, s_empty : std_logic;
+ signal r_ack, r_err : std_logic;
+ signal r_dat : t_wishbone_data;
begin
-
- slave_o <= r_slave;
- master_o <= r_master;
+ sp : wb_skidpad
+ generic map(
+ g_adrbits => c_wishbone_address_width
+ )
+ Port map(
+ clk_i => clk_sys_i,
+ rst_n_i => rst_n_i,
+ push_i => s_push,
+ pop_i => s_pop,
+ full_o => s_full,
+ empty_o => s_empty,
+ adr_i => slave_i.adr,
+ dat_i => slave_i.dat,
+ sel_i => slave_i.sel,
+ we_i => slave_i.we,
+ adr_o => master_o.adr,
+ dat_o => master_o.dat,
+ sel_o => master_o.sel,
+ we_o => master_o.we
+ );
+
+
+ slave_o.ack <= r_ack;
+ slave_o.err <= r_err;
+ slave_o.dat <= r_dat;
+
+ s_pop <= not master_i.stall;
+ s_push <= slave_i.cyc and slave_i.stb and not s_full;
+ slave_o.stall <= s_full;
+ master_o.stb <= not s_empty;
+ master_o.cyc <= slave_i.cyc;
+
main : process(clk_sys_i, rst_n_i) is
begin
if rst_n_i = '0' then
- r_slave <= cc_dummy_slave_out;
- r_master <= cc_dummy_master_out;
- r_slave.stall <= '0';
+ r_ack <= '0';
+ r_err <= '0';
+ r_dat <= (others => '0');
elsif rising_edge(clk_sys_i) then
-- no flow control on ack/err
- r_slave <= master_i;
-
- -- either we are accepting data (stb=0) or pushing data (stb=1)
- if r_master.stb = '0' then
- r_master <= slave_i;
- r_master.stb <= slave_i.cyc and slave_i.stb;
- r_slave.stall <= slave_i.cyc and slave_i.stb;
- else
- r_master.stb <= r_master.stb and master_i.stall;
- r_slave.stall <= r_master.stb and master_i.stall;
- end if;
-
+ r_ack <= master_i.ack;
+ r_err <= master_i.err;
+ r_dat <= master_i.dat;
end if;
end process;
diff --git a/modules/wishbone/wbgenplus/Manifest.py b/modules/wishbone/wbgenplus/Manifest.py
index 61622b747ff052e2df9b52ca14c3e7ec006964a0..658ecc0fddd225295c5ca3ec51811e74a7b335ae 100644
--- a/modules/wishbone/wbgenplus/Manifest.py
+++ b/modules/wishbone/wbgenplus/Manifest.py
@@ -1,5 +1,4 @@
-files = ["wb_skidpad.vhd",
- "wbgenplus_pkg.vhd",
+files = ["wbgenplus_pkg.vhd",
]
diff --git a/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd b/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd
index dd39c5a65cf84e1815a0aa8bf045836145b519db..5957bc20df72d63c137d88cc4ca0da2b7c42586f 100644
--- a/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd
+++ b/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd
@@ -4,33 +4,6 @@ use ieee.numeric_std.all;
package wbgenplus_pkg is
- component wb_skidpad is
- generic(
- g_adrbits : natural := 32 --Number of bits in adr
- );
- Port(
- clk_i : std_logic;
- rst_n_i : std_logic;
-
- push_i : in std_logic;
- pop_i : in std_logic;
- full_o : out std_logic;
- empty_o : out std_logic;
-
- adr_i : in std_logic_vector(g_adrbits-1 downto 0);
- dat_i : in std_logic_vector(32-1 downto 0);
- sel_i : in std_logic_vector(4-1 downto 0);
- we_i : in std_logic;
-
- adr_o : out std_logic_vector(g_adrbits-1 downto 0);
- dat_o : out std_logic_vector(32-1 downto 0);
- sel_o : out std_logic_vector(4-1 downto 0);
- we_o : out std_logic
-
-
- );
- end component;
-
type matrix is array(natural range <>, natural range <>) of std_logic;
-- assign row
diff --git a/modules/wishbone/wishbone_pkg.vhd b/modules/wishbone/wishbone_pkg.vhd
index 290f22f9b2a339ba679dfa6dc7291b01d570a7a2..5fad8b1a8cb6316ffc70b33f181a1b37bef420da 100644
--- a/modules/wishbone/wishbone_pkg.vhd
+++ b/modules/wishbone/wishbone_pkg.vhd
@@ -384,6 +384,32 @@ package wishbone_pkg is
master_o : out t_wishbone_master_out);
end component;
+ -- skidpad. acts like a fifo in wb flow control, but costs less
+ component wb_skidpad is
+ generic(
+ g_adrbits : natural := 32
+ );
+ Port(
+ clk_i : std_logic;
+ rst_n_i : std_logic;
+
+ push_i : in std_logic;
+ pop_i : in std_logic;
+ full_o : out std_logic;
+ empty_o : out std_logic;
+
+ adr_i : in std_logic_vector(g_adrbits-1 downto 0);
+ dat_i : in std_logic_vector(32-1 downto 0);
+ sel_i : in std_logic_vector(4-1 downto 0);
+ we_i : in std_logic;
+
+ adr_o : out std_logic_vector(g_adrbits-1 downto 0);
+ dat_o : out std_logic_vector(32-1 downto 0);
+ sel_o : out std_logic_vector(4-1 downto 0);
+ we_o : out std_logic
+ );
+ end component;
+
component sdb_rom is
generic(
g_layout : t_sdb_record_array;