diff --git a/modules/wishbone/Manifest.py b/modules/wishbone/Manifest.py
index 38f20c899fb10c2bf093c63c4d062db3ff3b416c..3328309d7a40283008448914051d31066a5f512a 100644
--- a/modules/wishbone/Manifest.py
+++ b/modules/wishbone/Manifest.py
@@ -12,7 +12,7 @@ modules =  { "local" : [
   "wb_vic",
   "wb_spi",
   "wb_crossbar",
-  "wb_reg_link",
+  "wb_register",
   "wb_irq",
   "wb_lm32",
   "wb_slave_adapter",
diff --git a/modules/wishbone/wb_reg_link/Manifest.py b/modules/wishbone/wb_reg_link/Manifest.py
deleted file mode 100644
index 253e4a6042a28ecc2ca0d9c6c08df7e6c444be85..0000000000000000000000000000000000000000
--- a/modules/wishbone/wb_reg_link/Manifest.py
+++ /dev/null
@@ -1,4 +0,0 @@
-files = [
-  "xwb_register_link.vhd",
-  "wb_skidpad.vhd",
-  ]
diff --git a/modules/wishbone/wb_register/Manifest.py b/modules/wishbone/wb_register/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..2959c0cfdeee7ee77bb63e92f73d7eeb2e112925
--- /dev/null
+++ b/modules/wishbone/wb_register/Manifest.py
@@ -0,0 +1,4 @@
+files = [
+    "xwb_register_link.vhd",
+    "wb_skidpad.vhd",
+]
diff --git a/modules/wishbone/wb_reg_link/wb_skidpad.vhd b/modules/wishbone/wb_register/wb_skidpad.vhd
similarity index 100%
rename from modules/wishbone/wb_reg_link/wb_skidpad.vhd
rename to modules/wishbone/wb_register/wb_skidpad.vhd
diff --git a/modules/wishbone/wb_reg_link/xwb_register_link.vhd b/modules/wishbone/wb_register/xwb_register_link.vhd
similarity index 97%
rename from modules/wishbone/wb_reg_link/xwb_register_link.vhd
rename to modules/wishbone/wb_register/xwb_register_link.vhd
index c5e61dfbcd2407dc73ff53edc9cb9622aad7aa32..94d839404d286553cf994b0b1002cc5c33c33064 100644
--- a/modules/wishbone/wb_reg_link/xwb_register_link.vhd
+++ b/modules/wishbone/wb_register/xwb_register_link.vhd
@@ -6,7 +6,7 @@
 -- Author     : Wesley W. Terpstra
 -- Company    : GSI
 -- Created    : 2013-12-16
--- Last update: 2018-11-16
+-- Last update: 2018-11-19
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -69,7 +69,7 @@ begin
       g_slave_use_struct   => TRUE,
       g_slave_mode         => g_WB_IN_MODE,
       g_slave_granularity  => g_WB_IN_GRANULARITY,
-      g_master_mode        => PIPELINED,
+      g_master_mode        => CLASSIC,
       g_master_granularity => BYTE)
     port map (
       clk_sys_i  => clk_sys_i,
@@ -83,7 +83,7 @@ begin
     generic map (
       g_master_use_struct  => TRUE,
       g_slave_use_struct   => TRUE,
-      g_slave_mode         => PIPELINED,
+      g_slave_mode         => CLASSIC,
       g_slave_granularity  => BYTE,
       g_master_mode        => g_WB_OUT_MODE,
       g_master_granularity => g_WB_OUT_GRANULARITY)