diff --git a/modules/common/Manifest.py b/modules/common/Manifest.py
index 2d4ad63c8558c0df32274bdf7de8801fc18f80aa..239292656d26c705659edce9b7036dc0b7503425 100644
--- a/modules/common/Manifest.py
+++ b/modules/common/Manifest.py
@@ -1,29 +1,32 @@
-files = [ "gencores_pkg.vhd",
- "gc_crc_gen.vhd",
- "gc_moving_average.vhd",
- "gc_delay_line.vhd",
- "gc_extend_pulse.vhd",
- "gc_delay_gen.vhd",
- "gc_dual_pi_controller.vhd",
- "gc_reset.vhd",
- "gc_serial_dac.vhd",
- "gc_sync_ffs.vhd",
- "gc_arbitrated_mux.vhd",
- "gc_pulse_synchronizer.vhd",
- "gc_pulse_synchronizer2.vhd",
- "gc_frequency_meter.vhd",
- "gc_rr_arbiter.vhd",
- "gc_prio_encoder.vhd",
- "gc_word_packer.vhd",
- "gc_i2c_slave.vhd",
- "gc_glitch_filt.vhd",
- "gc_dyn_glitch_filt.vhd",
- "gc_comparator.vhd",
- "gc_big_adder.vhd",
- "gc_fsm_watchdog.vhd",
- "gc_bicolor_led_ctrl.vhd",
- "gc_sync_register.vhd",
- "gc_single_reset_gen.vhd",
- "gc_async_signals_input_stage.vhd",
- "gc_dec_8b10b.vhd"
- ];
+files = [
+ "gencores_pkg.vhd",
+ "gc_crc_gen.vhd",
+ "gc_moving_average.vhd",
+ "gc_delay_line.vhd",
+ "gc_extend_pulse.vhd",
+ "gc_delay_gen.vhd",
+ "gc_dual_pi_controller.vhd",
+ "gc_reset.vhd",
+ "gc_serial_dac.vhd",
+ "gc_sync_ffs.vhd",
+ "gc_arbitrated_mux.vhd",
+ "gc_pulse_synchronizer.vhd",
+ "gc_pulse_synchronizer2.vhd",
+ "gc_frequency_meter.vhd",
+ "gc_rr_arbiter.vhd",
+ "gc_prio_encoder.vhd",
+ "gc_word_packer.vhd",
+ "gc_i2c_slave.vhd",
+ "gc_glitch_filt.vhd",
+ "gc_dyn_glitch_filt.vhd",
+ "gc_comparator.vhd",
+ "gc_big_adder.vhd",
+ "gc_fsm_watchdog.vhd",
+ "gc_bicolor_led_ctrl.vhd",
+ "gc_sync_register.vhd",
+ "gc_single_reset_gen.vhd",
+ "gc_async_signals_input_stage.vhd",
+ "gc_dec_8b10b.vhd"
+ "gc_dyn_extend_pulse.vhd",
+ "gc_ds182x_interface.vhd",
+];
diff --git a/modules/common/gc_ds182x_interface.vhd b/modules/common/gc_ds182x_interface.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..91684239085fd2952791ab7a12d5df937df7cbd5
--- /dev/null
+++ b/modules/common/gc_ds182x_interface.vhd
@@ -0,0 +1,572 @@
+---------------------------------------------------------------------------------------------------
+-- |
+-- one wire temperature & unique id interface for DS1822 and DS1820 |
+-- |
+---------------------------------------------------------------------------------------------------
+-- File gc_ds182x_interface.vhd |
+-- |
+-- Description Interface with the serial ID + Thermometer DS1822, DS1820 |
+-- Notes: Started from the DS2401 interface. |
+-- |
+-- Authors Pablo Antonio Alvarez Sanchez |
+---------------------------------------------------------------------------------------------------
+
+---------------------------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE |
+-- ------------------------------------ |
+-- This source file is free software; you can redistribute it and/or modify it under the terms of |
+-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
+-- version 2.1 of the License, or (at your option) any later version. |
+-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
+-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
+-- See the GNU Lesser General Public License for more details. |
+-- You should have received a copy of the GNU Lesser General Public License along with this |
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
+---------------------------------------------------------------------------------------------------
+
+--=================================================================================================
+-- Libraries & Packages
+--=================================================================================================
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+
+--=================================================================================================
+-- Entity declaration for fmc_masterFIP_core
+--=================================================================================================
+entity gc_ds182x_interface is
+ generic
+ (freq : integer := 40); -- clk frequency in MHz
+ port
+ (clk_i : in std_logic;
+ rst_n_i : in std_logic;
+ pps_p_i : in std_logic; -- pulse per second (for temperature read)
+ onewire_b : inout std_logic; -- IO to be connected to the chip(DS1820/DS1822)
+ id_o : out std_logic_vector(63 downto 0); -- id_o value
+ temper_o : out std_logic_vector(15 downto 0); -- temperature value (refreshed every second)
+ id_read_o : out std_logic; -- id_o value is valid_o
+ id_ok_o : out std_logic); -- Same as id_read_o, but not reset with rst_n_i
+end gc_ds182x_interface;
+
+
+--=================================================================================================
+-- architecture declaration
+--=================================================================================================
+architecture rtl of gc_ds182x_interface is
+
+ -- time slot constants according to specs https://www.maximintegrated.com/en/app-notes/index.mvp/id/162
+ constant SLOT_CNT_START : unsigned(15 downto 0) := to_unsigned(0*freq/40, 16);
+ constant SLOT_CNT_START_PLUSONE : unsigned(15 downto 0) := SLOT_CNT_START + 1;
+ constant SLOT_CNT_SET : unsigned(15 downto 0) := to_unsigned(60*freq/40, 16);
+ constant SLOT_CNT_RD : unsigned(15 downto 0) := to_unsigned(600*freq/40, 16);
+ constant SLOT_CNT_STOP : unsigned(15 downto 0) := to_unsigned(3600*freq/40, 16);
+ constant SLOT_CNT_PRESTOP : unsigned(15 downto 0) := to_unsigned((3600-60)*freq/40, 16);
+
+ constant READ_ID_HEADER : std_logic_vector(7 downto 0) := X"33";
+ constant CONVERT_HEADER : std_logic_vector(7 downto 0) := X"44";
+ constant READ_TEMPER_HEADER : std_logic_vector(7 downto 0) := X"BE";
+ constant SKIPHEADER : std_logic_vector(7 downto 0) := X"CC";
+
+ constant ID_LEFT : integer := 71;
+ constant ID_RIGHT : integer := 8;
+ constant TEMPER_LEFT : integer := 15;
+ constant TEMPER_RIGHT : integer := 0;
+ constant TEMPER_DONE_BIT : std_logic := '0'; -- The serial line is asserted to this value by the
+ -- DS1820/DS1822 when the temperature conversion is ready
+ constant TEMPER_LGTH : unsigned(7 downto 0) := to_unsigned(72, 8);
+ constant ID_LGTH : unsigned(7 downto 0) := to_unsigned(64, 8);
+
+ type op_fsm_t is (READ_ID_OP, SKIP_ROM_OP1, CONV_OP1, CONV_OP2, SKIP_ROM_OP2, READ_TEMP_OP);
+ type cm_fsm_t is (RST_CM, PREP_WR_CM, WR_CM, PREP_RD_CM, RD_CM, IDLE_CM);
+
+ signal bit_top, bit_cnt : unsigned(7 downto 0);
+ signal do_read_bit, do_write_bit, do_rst : std_logic;
+ signal slot_cnt : unsigned(15 downto 0);
+ signal start_p, end_p, set_value, read_value, init_pulse : std_logic;
+ signal state_op, nxt_state_op : op_fsm_t;
+ signal state_cm, nxt_state_cm : cm_fsm_t;
+
+ signal crc_vec, header : std_logic_vector(7 downto 0);
+ signal crc_ok, init, pre_read_p, i_id_read : std_logic;
+ signal load_temper, load_id, cm_only, pps_p_d : std_logic;
+
+ signal serial_id_out, nx_serial_id_out, nx_serial_id_oe : std_logic;
+ signal i_serial_id_oe, serial_idr : std_logic;
+ signal end_wr_cm, end_rd_cm, inc_bit_cnt, rst_bit_cnt : std_logic;
+ signal shift_header, id_cm_reg : std_logic;
+ signal cm_reg : std_logic_vector(71 downto 0);
+ signal shifted_header : std_logic_vector(7 downto 0);
+ signal pre_init_p : std_logic;
+
+--=================================================================================================
+-- architecture begin
+--=================================================================================================
+begin
+
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ -- Serial data line in tri-state, when not writing data out
+ onewire_b <= serial_id_out when i_serial_id_oe = '1' else 'Z';
+
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ -- pps_p_i 1 clock tick delay
+ pps_p_iDelay: process (clk_i)
+ begin
+ if rising_edge(clk_i) then
+ pps_p_d <= pps_p_i;
+ end if;
+ end process;
+
+
+
+---------------------------------------------------------------------------------------------------
+-- operations FSM --
+---------------------------------------------------------------------------------------------------
+ op_fsm_transitions: process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if rst_n_i = '0' then
+ state_op <= READ_ID_OP;
+ else
+ state_op <= nxt_state_op;
+ end if;
+ end if;
+ end process;
+
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ op_fsm_states: process(state_op, pps_p_i, crc_ok)
+ begin
+ nxt_state_op <= READ_ID_OP;
+ case state_op is
+
+ when READ_ID_OP =>
+ if pps_p_i = '1' and crc_ok = '1' then
+ nxt_state_op <= CONV_OP1;
+ else
+ nxt_state_op <= state_op;
+ end if;
+
+ when CONV_OP1 =>
+ if pps_p_i = '1' then
+ nxt_state_op <= SKIP_ROM_OP1;
+ else
+ nxt_state_op <= state_op;
+ end if;
+
+ when SKIP_ROM_OP1 =>
+ if pps_p_i = '1' then
+ nxt_state_op <= READ_TEMP_OP;
+ else
+ nxt_state_op <= state_op;
+ end if;
+
+ when READ_TEMP_OP =>
+ if pps_p_i = '1' then
+ nxt_state_op <= SKIP_ROM_OP2;
+ else
+ nxt_state_op <= state_op;
+ end if;
+
+ when SKIP_ROM_OP2 =>
+ if pps_p_i = '1' then
+ nxt_state_op <= CONV_OP2;
+ else
+ nxt_state_op <= state_op;
+ end if;
+
+ when CONV_OP2 =>
+ if pps_p_i = '1' then
+ nxt_state_op <= SKIP_ROM_OP1;
+ else
+ nxt_state_op <= state_op;
+ end if;
+
+ end case;
+ end process;
+
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ op_fsm_outputs:process(state_op, state_cm, crc_ok, pps_p_i, cm_only)
+ begin
+ header <= READ_ID_HEADER;
+ bit_top <= ID_LGTH;
+ load_temper <= '0';
+ load_id <= '0';
+ cm_only <= '0';
+
+ case state_op is
+
+ when READ_ID_OP =>
+ header <= READ_ID_HEADER;
+ bit_top <= ID_LGTH;
+ if state_cm = IDLE_CM then
+ load_id <= crc_ok;
+ end if;
+
+ when CONV_OP1 =>
+ header <= CONVERT_HEADER;
+ cm_only <= '1';
+
+ when SKIP_ROM_OP1 =>
+ header <= SKIPHEADER;
+ cm_only <= '1';
+
+ when READ_TEMP_OP =>
+ header <= READ_TEMPER_HEADER;
+ bit_top <= TEMPER_LGTH;
+ if state_cm = IDLE_CM then
+ load_temper <= crc_ok and pps_p_i;
+ end if;
+
+ when SKIP_ROM_OP2 =>
+ header <= SKIPHEADER;
+ cm_only <= '1';
+
+ when CONV_OP2 =>
+ header <= CONVERT_HEADER;
+ cm_only <= '1';
+
+ when others => null;
+
+ end case;
+ end process;
+
+
+
+---------------------------------------------------------------------------------------------------
+-- commands FSM --
+---------------------------------------------------------------------------------------------------
+ cm_fsm_transitions: process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if rst_n_i = '0' then
+ state_cm <= RST_CM;
+ else
+ state_cm <= nxt_state_cm;
+ end if;
+ end if;
+ end process;
+
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ cm_fsm_states: process(state_cm, start_p, end_wr_cm, end_rd_cm, crc_ok, state_op, cm_only, pps_p_d)
+ begin
+ nxt_state_cm <= RST_CM;
+ case state_cm is
+ when RST_CM =>
+ if start_p = '1' then
+ nxt_state_cm <= PREP_WR_CM;
+ else
+ nxt_state_cm <= state_cm;
+ end if;
+
+ when PREP_WR_CM =>
+ if start_p = '1' then
+ nxt_state_cm <= WR_CM;
+ else
+ nxt_state_cm <= state_cm;
+ end if;
+
+ when WR_CM =>
+ if end_wr_cm = '1' then
+ if cm_only = '0' then
+ nxt_state_cm <= PREP_RD_CM;
+ else
+ nxt_state_cm <= IDLE_CM;
+ end if;
+ else
+ nxt_state_cm <= state_cm;
+ end if;
+
+ when PREP_RD_CM =>
+ if start_p = '1' then
+ nxt_state_cm <= RD_CM;
+ else
+ nxt_state_cm <= state_cm;
+ end if;
+
+ when RD_CM =>
+ if end_rd_cm = '1' then
+ nxt_state_cm <= IDLE_CM;
+ else
+ nxt_state_cm <= state_cm;
+ end if;
+
+ when IDLE_CM =>
+ if state_op = READ_ID_OP then
+ if crc_ok = '0' then
+ nxt_state_cm <= RST_CM;
+ else
+ nxt_state_cm <= state_cm;
+ end if;
+ elsif state_op = READ_TEMP_OP then -- At this moment I will send a Conv temper_o command
+ if pps_p_d = '1' then
+ nxt_state_cm <= PREP_WR_CM;
+ else
+ nxt_state_cm <= state_cm;
+ end if;
+ elsif (state_op = CONV_OP1) or (state_op = CONV_OP2) then -- At this moment I will restart a temper_o read
+ if pps_p_d = '1' then
+ nxt_state_cm <= PREP_WR_CM;
+ else
+ nxt_state_cm <= state_cm;
+ end if;
+ elsif (state_op = SKIP_ROM_OP1) or (state_op = SKIP_ROM_OP2) then -- At this moment I will restart
+ if pps_p_d = '1' then
+ nxt_state_cm <= RST_CM;
+ else
+ nxt_state_cm <= state_cm;
+ end if;
+ else
+ nxt_state_cm <= state_cm;
+ end if;
+ end case;
+ end process;
+
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ cm_fsm_outputs:process(state_cm, bit_cnt, pre_read_p, crc_vec, start_p,
+ shifted_header, init_pulse, read_value, pre_init_p)
+ begin
+ inc_bit_cnt <= '0';
+ nx_serial_id_out <= '0';
+ shift_header <= '0';
+ id_cm_reg <= '0';
+ nx_serial_id_oe <= '0';
+ rst_bit_cnt <= '0';
+ init <= '0';
+ crc_ok <= '0';
+ case state_cm is
+ when RST_CM =>
+ rst_bit_cnt <= '1';
+ nx_serial_id_out <= '0';
+ nx_serial_id_oe <= '1';
+ init <= start_p;
+ when PREP_WR_CM =>
+ rst_bit_cnt <= start_p;
+ nx_serial_id_oe <= '0';
+ nx_serial_id_out <= '0';
+ when WR_CM =>
+ shift_header <= start_p;
+ inc_bit_cnt <= start_p;
+ rst_bit_cnt <= '0';
+ nx_serial_id_out <= shifted_header(0) and (not init_pulse);
+ if bit_cnt < to_unsigned(7, bit_cnt'length) then
+ nx_serial_id_oe <= not pre_init_p;
+ else
+ nx_serial_id_oe <= not pre_read_p;
+ end if;
+ when PREP_RD_CM =>
+ rst_bit_cnt <= start_p;
+ nx_serial_id_oe <= '0';
+ nx_serial_id_out <= '0';
+ when RD_CM =>
+ inc_bit_cnt <= start_p;
+ rst_bit_cnt <= '0';
+ nx_serial_id_out <= not init_pulse;
+ id_cm_reg <= read_value;
+ nx_serial_id_oe <= init_pulse;
+ when IDLE_CM =>
+ if crc_vec = x"00" then
+ crc_ok <= '1';
+ else
+ crc_ok <= '0';
+ end if;
+ init <= '1';
+ end case;
+ end process;
+
+
+
+---------------------------------------------------------------------------------------------------
+-- time slots --
+---------------------------------------------------------------------------------------------------
+ -- Generates time slots
+ -- Reset pulse
+ -- Read time slot
+ -- Write time slots
+ process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if rst_n_i = '0' then
+ slot_cnt(slot_cnt'left) <= '1';
+ slot_cnt(slot_cnt'left -1 downto 0) <= (others => '0');
+ start_p <= '0';
+ end_p <= '0';
+ set_value <= '0';
+ read_value <= '0';
+ init_pulse <= '0';
+ pre_init_p <= '0';
+ pre_read_p <= '0';
+ else
+
+ -- Slot counter
+ if init = '1' then
+ slot_cnt(slot_cnt'left) <= '1';
+ slot_cnt(slot_cnt'left - 1 downto 0) <= (others => '0');
+ elsif slot_cnt = SLOT_CNT_STOP then
+ slot_cnt <= (others => '0');
+ else
+ slot_cnt <= slot_cnt + 1;
+ end if;
+
+ -- Time slot start pulse
+ if slot_cnt = SLOT_CNT_START then
+ start_p <= '1';
+ else
+ start_p <= '0';
+ end if;
+
+ if ((slot_cnt > SLOT_CNT_START) and (slot_cnt < SLOT_CNT_SET)) then
+ init_pulse <= '1';
+ else
+ init_pulse <= '0';
+ end if;
+
+ if ((slot_cnt > SLOT_CNT_PRESTOP) and (slot_cnt < SLOT_CNT_STOP)) then
+ pre_init_p <= '1';
+ else
+ pre_init_p <= '0';
+ end if;
+
+ if (((slot_cnt > SLOT_CNT_PRESTOP) and (slot_cnt <= SLOT_CNT_STOP)) or
+ (slot_cnt <= SLOT_CNT_START_PLUSONE)) then
+ pre_read_p <= '1';
+ else
+ pre_read_p <= '0';
+ end if;
+
+ -- End of time slot pulse
+ if slot_cnt = SLOT_CNT_START then
+ end_p <= '1';
+ else
+ end_p <= '0';
+ end if;
+
+ -- Pulse to write value on serial link
+ if slot_cnt = SLOT_CNT_SET then
+ set_value <= '1';
+ else
+ set_value <= '0';
+ end if;
+
+ -- Pulse to read value on serial link
+ if slot_cnt = SLOT_CNT_RD then
+ read_value <= '1';
+ else
+ read_value <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+
+---------------------------------------------------------------------------------------------------
+-- serdes --
+---------------------------------------------------------------------------------------------------
+ -- Data serializer bit counter
+ BitCnt_p:process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if rst_n_i = '0' then
+ bit_cnt <= (others => '0');
+ else
+ if rst_bit_cnt = '1' then
+ bit_cnt <= (others => '0');
+ elsif inc_bit_cnt = '1' then
+ bit_cnt <= bit_cnt + 1;
+ end if;
+ end if;
+ end if;
+ end process;
+
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ -- Data serializer shift register
+ ShiftReg_p:process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if rst_n_i = '0' then
+ shifted_header <= READ_ID_HEADER;
+ cm_reg <= (others => '0');
+ serial_idr <= '0';
+ serial_id_out <= '0';
+ i_serial_id_oe <= '0';
+ id_o <= (others => '0');
+ i_id_read <= '0';
+ id_read_o <= '0';
+ crc_vec <= (others => '0');
+ temper_o <= (others => '0');
+ else
+ -- Samples serial input
+ serial_idr <= onewire_b;
+
+ -- Shifts command out
+ if init = '1' then
+ shifted_header <= header;
+ elsif shift_header = '1' then
+ shifted_header(shifted_header'left-1 downto 0) <= shifted_header(shifted_header'left downto 1);
+ shifted_header(shifted_header'left) <= '0';
+ end if;
+
+ -- Computes CRC on read data (include the received CRC itself, if no errror crc_vec = X"00")
+ if init = '1' then
+ crc_vec <= (others => '0');
+ elsif id_cm_reg = '1' then
+ crc_vec(0) <= serial_idr xor crc_vec(7);
+ crc_vec(3 downto 1) <= crc_vec(2 downto 0);
+ crc_vec(4) <= (serial_idr xor crc_vec(7)) xor crc_vec(3);
+ crc_vec(5) <= (serial_idr xor crc_vec(7)) xor crc_vec(4);
+ crc_vec(7 downto 6) <= crc_vec(6 downto 5);
+ end if;
+
+ -- Stores incoming data
+ if (id_cm_reg = '1') then
+ cm_reg(cm_reg'left - 1 downto 0) <= cm_reg(cm_reg'left downto 1);
+ cm_reg(cm_reg'left) <= serial_idr;
+ end if;
+
+ -- Updates serial output data
+ serial_id_out <= nx_serial_id_out;
+
+ -- Updates serial output enable
+ i_serial_id_oe <= nx_serial_id_oe;
+
+ -- Stores id_o in register
+ if (load_id = '1')then
+ i_id_read <= '1';
+ id_o <= cm_reg(ID_LEFT downto ID_RIGHT);
+ end if;
+
+ -- Stores temperature in register
+ if (load_temper = '1')then
+ temper_o <= cm_reg(TEMPER_LEFT downto TEMPER_RIGHT);
+ end if;
+
+ -- Delays id_o read
+ id_read_o <= i_id_read;
+ end if;
+ end if;
+ end process;
+
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ -- Value on id_o port is valid_o
+ process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ if state_cm = IDLE_CM then
+ id_ok_o <= crc_ok;
+ end if;
+ end if;
+ end process;
+
+-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ -- Detects end of read or end of write command
+ end_wr_cm <= '1' when (bit_cnt = to_unsigned(7, bit_cnt'length)) and (inc_bit_cnt = '1') else '0';
+ end_rd_cm <= '1' when (bit_cnt = bit_top) else '0';
+
+
+end rtl;
+--=================================================================================================
+-- architecture end
+--=================================================================================================
+---------------------------------------------------------------------------------------------------
+-- E N D O F F I L E
+---------------------------------------------------------------------------------------------------
diff --git a/modules/common/gc_dyn_extend_pulse.vhd b/modules/common/gc_dyn_extend_pulse.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b1ad687405ba21cd33b99ec31cd9658fe3e883fc
--- /dev/null
+++ b/modules/common/gc_dyn_extend_pulse.vhd
@@ -0,0 +1,95 @@
+-------------------------------------------------------------------------------
+-- Title : Pulse width extender
+-- Project : General Cores library
+-------------------------------------------------------------------------------
+-- File : gc_extend_pulse.vhd
+-- Author : Tomasz Wlostowski
+-- Company : CERN
+-- Created : 2009-09-01
+-- Last update: 2012-06-19
+-- Platform : FPGA-generic
+-- Standard : VHDL '93
+-------------------------------------------------------------------------------
+-- Description:
+-- Synchronous pulse extender. Generates a pulse of programmable width upon
+-- detection of a rising edge in the input.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2009-2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2009-09-01 0.9 twlostow Created
+-- 2011-04-18 1.0 twlostow Added comments & header
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.NUMERIC_STD.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.genram_pkg.all;
+
+entity gc_dyn_extend_pulse is
+ generic
+ (
+ -- Number of bits of the len_i input
+ g_len_width : natural := 10
+ );
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+ -- input pulse (synchronous to clk_i)
+ pulse_i : in std_logic;
+ -- output pulse length in clk_i cycles
+ len_i : in std_logic_vector(g_len_width-1 downto 0);
+ -- extended output pulse
+ extended_o : out std_logic := '0');
+end gc_dyn_extend_pulse;
+
+architecture rtl of gc_dyn_extend_pulse is
+
+ signal cntr : unsigned(g_len_width-1 downto 0);
+ signal extended_int : std_logic;
+
+begin -- rtl
+
+ extend : process (clk_i, rst_n_i)
+ begin -- process extend
+ if rst_n_i = '0' then -- asynchronous reset (active low)
+ extended_int <= '0';
+ cntr <= (others => '0');
+ elsif clk_i'event and clk_i = '1' then -- rising clock edge
+ if(pulse_i = '1') then
+ extended_int <= '1';
+ cntr <= unsigned(len_i) - 2;
+ elsif cntr /= to_unsigned(0, cntr'length) then
+ cntr <= cntr - 1;
+ else
+ extended_int <= '0';
+ end if;
+ end if;
+ end process extend;
+
+ extended_o <= pulse_i or extended_int;
+
+end rtl;
+
diff --git a/modules/common/gencores_pkg.vhd b/modules/common/gencores_pkg.vhd
index 4e6d39fe7cf136212a2e605b5860539adb4fa1bc..af670d43cc39a352d013df19f52264c5418522ca 100644
--- a/modules/common/gencores_pkg.vhd
+++ b/modules/common/gencores_pkg.vhd
@@ -6,6 +6,7 @@
-- Author : Tomasz Wlostowski
-- Theodor-Adrian Stana
-- Matthieu Cattin
+-- Evangelia Gousiou
-- Dimitrios Lampridis
-- Company : CERN
-- Created : 2009-09-01
@@ -37,6 +38,15 @@
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
+-- Revisions :
+-- Date Version Author Description
+-- 2009-09-01 0.9 twlostow Created
+-- 2011-04-18 1.0 twlostow Added comments & header
+-- 2013-11-20 1.1 tstana Added glitch filter and I2C slave
+-- 2014-03-14 1.2 mcattin Added dynamic glitch filter
+-- 2014-03-20 1.3 mcattin Added bicolor led controller
+-- 2016-09-26 1.4 egousiou Added one-wire DS182x interface
+-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
@@ -63,6 +73,17 @@ package gencores_pkg is
extended_o : out std_logic);
end component;
+ component gc_dyn_extend_pulse is
+ generic (
+ g_len_width : natural := 10);
+ port (
+ clk_i : in std_logic;
+ rst_n_i : in std_logic;
+ pulse_i : in std_logic;
+ len_i : in std_logic_vector(g_len_width-1 downto 0);
+ extended_o : out std_logic := '0');
+ end component;
+
------------------------------------------------------------------------------
-- CRC generator
------------------------------------------------------------------------------
@@ -276,6 +297,7 @@ package gencores_pkg is
);
end component;
+
------------------------------------------------------------------------------
-- Round robin arbiter
------------------------------------------------------------------------------
@@ -342,8 +364,7 @@ package gencores_pkg is
-- 0 - SCL and SDA lines are passed only through synchronizer
-- 1 - one clk_i glitches filtered
-- 2 - two clk_i glitches filtered
- g_gf_len : natural := 0;
- g_auto_addr_ack : boolean := FALSE
+ g_gf_len : natural := 0
);
port
(
@@ -518,6 +539,50 @@ package gencores_pkg is
signals_pN_o : out std_logic_vector(g_signal_num-1 downto 0));
end component;
+
+ ------------------------------------------------------------------------------
+ -- Priority encoder
+ ------------------------------------------------------------------------------
+ component gc_prio_encoder is
+ generic (
+ g_width : integer);
+ port (
+ d_i : in std_logic_vector(g_width-1 downto 0);
+ therm_o : out std_logic_vector(g_width-1 downto 0));
+ end component;
+
+ ------------------------------------------------------------------------------
+ -- Delay generator
+ ------------------------------------------------------------------------------
+ component gc_delay_gen is
+ generic(
+ g_delay_cycles : in natural;
+ g_data_width : in natural);
+
+ port(clk_i : in std_logic;
+ rst_n_i : in std_logic;
+ d_i : in std_logic_vector(g_data_width - 1 downto 0);
+ q_o : out std_logic_vector(g_data_width - 1 downto 0));
+ end component;
+
+ ------------------------------------------------------------------------------
+ -- One-wire interface to DS1820 and DS1822
+ ------------------------------------------------------------------------------
+ component gc_ds182x_interface is
+ generic
+ (freq : integer := 40);
+ port
+ (clk_i : in std_logic;
+ rst_n_i : in std_logic;
+ pps_p_i : in std_logic;
+ onewire_b : inout std_logic;
+ id_o : out std_logic_vector(63 downto 0);
+ temper_o : out std_logic_vector(15 downto 0);
+ id_read_o : out std_logic;
+ id_ok_o : out std_logic);
+ end component;
+
+
--============================================================================
-- Procedures and functions
--============================================================================
@@ -531,7 +596,6 @@ package gencores_pkg is
function f_gray_encode(x : std_logic_vector) return std_logic_vector;
function f_gray_decode(x : std_logic_vector; step : natural) return std_logic_vector;
function log2_ceil(N : natural) return positive;
-
function f_bool2int (b : boolean) return natural;
function f_int2bool (n : natural) return boolean;
@@ -647,6 +711,7 @@ package body gencores_pkg is
end if;
end;
+
------------------------------------------------------------------------------
-- Converts a boolean to natural integer (false -> 0, true -> 1)
------------------------------------------------------------------------------
@@ -671,4 +736,5 @@ package body gencores_pkg is
end if;
end;
+
end gencores_pkg;
diff --git a/modules/wishbone/wishbone_pkg.vhd b/modules/wishbone/wishbone_pkg.vhd
index b7dfdfafca5b8c48b47876637698f5823e5a3e50..342fabae62f84ce37e348b6218706cf07c8543fc 100644
--- a/modules/wishbone/wishbone_pkg.vhd
+++ b/modules/wishbone/wishbone_pkg.vhd
@@ -1174,7 +1174,7 @@ package wishbone_pkg is
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
- addr_last => x"00000000000000ff",
+ addr_last => x"000000000000ffff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"ffffffff",