diff --git a/sim/if_wb_master.svh b/sim/if_wb_master.svh
index 66dcc8c96b4afc5df7045b58bdea5db47854c86a..1a0bbeebea364047fd9eb8f71df731a61f316f0d 100644
--- a/sim/if_wb_master.svh
+++ b/sim/if_wb_master.svh
@@ -361,7 +361,6 @@ class CIWBMasterAccessor extends CWishboneAccessor;
endtask // clear
task put(ref wb_cycle_t xfer);
- // $display("WBMaster[%d]: PutCycle",g_data_width);
request_queue.push_back(xfer);
endtask // put
@@ -371,11 +370,12 @@ class CIWBMasterAccessor extends CWishboneAccessor;
endclass // CIWBMasterAccessor
- function CIWBMasterAccessor get_accessor();
- CIWBMasterAccessor tmp;
+ function automatic CIWBMasterAccessor get_accessor();
+ automatic CIWBMasterAccessor tmp;
tmp = new;
return tmp;
- endfunction // get_accessoror
+ endfunction // get_accessor
+
always@(posedge clk_i)
if(!rst_n_i)
diff --git a/sim/if_wb_slave.svh b/sim/if_wb_slave.svh
index 14034b53037dc985d9788cc710750d3832b52260..2db3dcef9df9550b0aeeb4fa754795020a67907c 100644
--- a/sim/if_wb_slave.svh
+++ b/sim/if_wb_slave.svh
@@ -58,13 +58,18 @@ interface IWishboneSlave
struct {
wb_cycle_type_t mode;
int gen_random_stalls;
+ int gen_random_errors;
int stall_min_duration;
int stall_max_duration;
real stall_prob;
+ real error_prob;
} settings;
+ int permanent_stall = 0;
function automatic int _poll(); return poll(); endfunction
+ function automatic int _permanent_stall_enable(); return permanent_stall_enable(); endfunction
+ function automatic int _permanent_stall_disable(); return permanent_stall_disable(); endfunction
task automatic _get(ref wb_cycle_t xfer); get(xfer); endtask
class CIWBSlaveAccessor extends CWishboneAccessor;
@@ -73,6 +78,14 @@ interface IWishboneSlave
return _poll();
endfunction
+ function automatic int permanent_stall_enable();
+ return _permanent_stall_enable();
+ endfunction
+
+ function automatic int permanent_stall_disable();
+ return _permanent_stall_disable();
+ endfunction
+
task get(ref wb_cycle_t xfer);
_get(xfer);
endtask
@@ -89,6 +102,17 @@ interface IWishboneSlave
return tmp;
endfunction // get_accessor
+ function automatic int permanent_stall_enable();
+ permanent_stall = 1;
+ $display("permanent stall ON");
+ return permanent_stall;
+ endfunction
+
+ function automatic int permanent_stall_disable();
+ permanent_stall = 0;
+ $display("permanent stall OFF");
+ return permanent_stall;
+ endfunction
function automatic int poll();
return c_queue.size() != 0;
@@ -152,7 +176,10 @@ interface IWishboneSlave
task pipelined_fsm();
- if(settings.gen_random_stalls)
+
+ if(permanent_stall)
+ stall <= 1;
+ else if(settings.gen_random_stalls)
gen_random_stalls();
else
stall <= 0;
@@ -174,6 +201,11 @@ interface IWishboneSlave
c_queue.push_back(current_cycle);
end
+ if(cyc && settings.gen_random_errors && probability_hit(settings.error_prob))
+ err <= 1;
+ else
+ err <= 0;
+
if(stb && we && !stall && cyc) begin
int oc, lzc, tzc;
@@ -238,4 +270,4 @@ interface IWishboneSlave
endinterface // IWishboneSlave
-`endif
\ No newline at end of file
+`endif
diff --git a/sim/if_wishbone_accessor.svh b/sim/if_wishbone_accessor.svh
index b0f789719d420305c934cf6589576cde971b3eb4..dd82ae5dc38070d43ffffb5731d7a1b9a3f7aa69 100644
--- a/sim/if_wishbone_accessor.svh
+++ b/sim/if_wishbone_accessor.svh
@@ -10,6 +10,7 @@ virtual class CWishboneAccessor extends CBusAccessor;
function new();
m_cycle_type = CLASSIC;
+ m_default_xfer_size = 4;
endfunction // new
virtual task set_mode(wb_cycle_type_t mode);
diff --git a/sim/simdrv_defs.svh b/sim/simdrv_defs.svh
index e7e04bc799491fe528f0dad39eca62781e9014f3..cb25c75a4e86d9c1f92632f7fc9674756d4e7845 100644
--- a/sim/simdrv_defs.svh
+++ b/sim/simdrv_defs.svh
@@ -15,11 +15,19 @@ typedef byte byte_array_t[];
virtual class CBusAccessor;
static int _null = 0;
+ int m_default_xfer_size;
+
+
+ task set_default_xfer_size(int default_size);
+ m_default_xfer_size = default_size;
+ endtask // set_default_xfer_size
+
+
pure virtual task writem(uint64_t addr[], uint64_t data[], input int size, ref int result);
pure virtual task readm(uint64_t addr[], ref uint64_t data[], input int size, ref int result);
- virtual task read(uint64_t addr, ref uint64_t data, input int size = 4, ref int result = _null);
+ virtual task read(uint64_t addr, ref uint64_t data, input int size = m_default_xfer_size, ref int result = _null);
int res;
uint64_t aa[1], da[];
@@ -31,7 +39,7 @@ virtual class CBusAccessor;
endtask
- virtual task write(uint64_t addr, uint64_t data, input int size = 4, ref int result = _null);
+ virtual task write(uint64_t addr, uint64_t data, input int size = m_default_xfer_size, ref int result = _null);
uint64_t aa[1], da[1];
aa[0] = addr;
da[0] = data;
@@ -101,4 +109,4 @@ static CSimUtils SimUtils;
-`endif
\ No newline at end of file
+`endif
diff --git a/sim/vhd_wishbone_master.svh b/sim/vhd_wishbone_master.svh
new file mode 100644
index 0000000000000000000000000000000000000000..87f6c252a910dbee189f23ebd8c5936715531af7
--- /dev/null
+++ b/sim/vhd_wishbone_master.svh
@@ -0,0 +1,61 @@
+`ifndef __VHD_WISHBONE_MASTER_INCLUDED
+ `define __VHD_WISHBONE_MASTER_INCLUDED
+
+`include "simdrv_defs.svh"
+`include "if_wb_master.svh"
+
+import wishbone_pkg::*;
+
+interface IVHDWishboneMaster
+ (
+ input clk_i,
+ input rst_n_i
+ );
+
+ parameter g_addr_width = 32;
+ parameter g_data_width = 32;
+
+ typedef virtual IWishboneMaster VIWishboneMaster;
+
+ IWishboneMaster #(g_addr_width, g_data_width) TheMaster (clk_i, rst_n_i);
+
+ t_wishbone_master_in in;
+ t_wishbone_master_out out;
+
+ modport master
+ (
+ input in,
+ output out
+ );
+
+ assign out.cyc = TheMaster.cyc;
+ assign out.stb = TheMaster.stb;
+ assign out.we = TheMaster.we;
+ assign out.sel = TheMaster.sel;
+ assign out.adr = TheMaster.adr;
+ assign out.dat = TheMaster.dat_o;
+
+ assign TheMaster.ack = in.ack;
+ assign TheMaster.stall = in.stall;
+ assign TheMaster.rty = in.rty;
+ assign TheMaster.err = in.err;
+ assign TheMaster.dat_i = in.dat;
+
+
+ function automatic CWishboneAccessor get_accessor();
+ automatic CWishboneAccessor acc = TheMaster.get_accessor();
+ return acc;
+ endfunction // get_accessor
+
+ initial begin
+ @(posedge rst_n_i);
+ @(posedge clk_i);
+
+ TheMaster.settings.addr_gran = BYTE;
+ TheMaster.settings.cyc_on_stall = 1;
+ end
+
+
+endinterface // IVHDWishboneMaster
+
+`endif // `ifndef __VHD_WISHBONE_MASTER_INCLUDED