diff --git a/modules/wishbone/Manifest.py b/modules/wishbone/Manifest.py
index 0cbed6bc35c98eac14de177d9b41ea2a0af3306c..e5452b423846666909970f1236d7a975db89bde6 100644
--- a/modules/wishbone/Manifest.py
+++ b/modules/wishbone/Manifest.py
@@ -1,17 +1,21 @@
 modules =  { "local" :
 	
 						[ 
-#						"wb_async_bridge",
+						"wb_async_bridge",
 						"wb_onewire_master",
 						"wb_i2c_master",
 						"wb_bus_fanout",
 						"wb_conmax",
+						"wb_dpram",
 						"wb_gpio_port",
 						"wb_simple_timer",
 						"wb_uart",
 						"wb_vic",
 						"wb_spi",
 						"wb_virtual_uart",
+						"wb_crossbar",
+						"wb_lm32",
+						"wb_slave_adapter",
 						"wbgen2"
 						 ]};
 
diff --git a/modules/wishbone/wb_slave_adapter/Manifest.py b/modules/wishbone/wb_slave_adapter/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..8245799d7c892376e3d4879cab435330ab4169e6
--- /dev/null
+++ b/modules/wishbone/wb_slave_adapter/Manifest.py
@@ -0,0 +1 @@
+files = ["wb_slave_adapter.vhd"]
diff --git a/modules/wishbone/wb_slave_adapter.vhd b/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
similarity index 97%
rename from modules/wishbone/wb_slave_adapter.vhd
rename to modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
index 1dcfc4aa0bc8c382d9dc2ff9090ba72c1ad3dfa6..be37af47610818c764b08330ab4c76748808c92e 100644
--- a/modules/wishbone/wb_slave_adapter.vhd
+++ b/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
@@ -177,7 +177,13 @@ begin  -- rtl
       end if;
       slave_out.stall <= '0';
     elsif(g_slave_mode = CLASSIC and g_master_mode = PIPELINED) then
-      master_out.stb <= slave_in.stb;
+
+      if(fsm_state = WAIT4ACK) then
+        master_out.stb <= '1';
+      else
+        master_out.stb <= slave_in.stb;
+      end if;
+      
       if(master_out.cyc = '1') then
         slave_out.stall <= '0';
       else
@@ -189,7 +195,7 @@ begin  -- rtl
     end if;
   end process;
 
-  master_out.dat <= slave_in.adr;
+  master_out.dat <= slave_in.dat;
   master_out.cyc <= slave_in.cyc;
   master_out.sel <= slave_in.sel;
   master_out.we  <= slave_in.we;