From 46e0f6dcb1bd0f8f60f8ca70e24622a695f387c3 Mon Sep 17 00:00:00 2001
From: Theodor Stana <t.stana@cern.ch>
Date: Mon, 7 Apr 2014 18:07:18 +0200
Subject: [PATCH] wb_i2c_bridge: Fix error in state-machine
The main state machine had an error whereby the wb_cyc and wb_stb
outputs were not assigned in the IDLE state.
This manifested itself as follows (output from telnet console):
%> writereg 1 100 0 # read to illegal address
Not acknowledged!
%> readreg 1 4 # read from legal address returns NACK
Not acknowledged
%> readreg 1 4 # next read from legal address returns right data
Read data: 01234567
The bug was because the first writereg started a WB transfer from
an unexisting address, threw an error and returned to IDLE without
releasing the wb_cyc and wb_stb outputs in the process. This meant
that on the readreg command, the WB write access would still be in
progress and only on the readreg command, an error would clear the
wb_cyc and wb_stb, which released the transfer.
The error has been fixed by placing the clearing of wb_cyc and wb_stb
in the IDLE state.
---
modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd b/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd
index 8b73424..7932437 100644
--- a/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd
+++ b/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd
@@ -47,7 +47,9 @@
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
--- 2013-02-28 Theodor Stana t.stana@cern.ch File created
+-- 2013-02-28 Theodor Stana File created
+-- 2014-04-07 Theodor Stana Fixed non-assigned WB CYC and STB signals
+-- in IDLE state
--==============================================================================
-- TODO: -
--==============================================================================
@@ -263,6 +265,9 @@ begin
adr_byte_cnt <= (others => '0');
dat_byte_cnt <= (others => '0');
wdt_rst <= '1';
+ wb_cyc <= '0';
+ wb_stb <= '0';
+ wb_we <= '0';
if (slv_addr_good_p = '1') then
tip_o <= '1';
slv_ack <= '1';
@@ -367,8 +372,6 @@ begin
state <= SYSMON_RD;
elsif (wb_err = '1') then
err_p_o <= '1';
- wb_cyc <= '0';
- wb_stb <= '0';
state <= IDLE;
end if;
--
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