From 2f75fcf8c88d383a23edd408a8a64c44c6d48f5b Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <w.terpstra@gsi.de>
Date: Thu, 21 Feb 2013 17:08:52 +0100
Subject: [PATCH] altera pcie: leave generated SDC constraints as a reference
only
---
modules/wishbone/wb_pcie/altera_pcie.sdc | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/modules/wishbone/wb_pcie/altera_pcie.sdc b/modules/wishbone/wb_pcie/altera_pcie.sdc
index e64906b..5a1ac5f 100644
--- a/modules/wishbone/wb_pcie/altera_pcie.sdc
+++ b/modules/wishbone/wb_pcie/altera_pcie.sdc
@@ -5,8 +5,8 @@
# testin bits are either static or treated asynchronously, cut the paths.
#set_false_path -to [get_pins -hierarchical {*hssi_pcie_hip|testin[*]} ]
# SERDES Digital Reset inputs are asynchronous
-set_false_path -to {*|altera_pcie_serdes:serdes|*|tx_digitalreset_reg0c[0]}
-set_false_path -to {*|altera_pcie_serdes:serdes|*|rx_digitalreset_reg0c[0]}
+#set_false_path -to {*|altera_pcie_serdes:serdes|*|tx_digitalreset_reg0c[0]}
+#set_false_path -to {*|altera_pcie_serdes:serdes|*|rx_digitalreset_reg0c[0]}
#
# The following multicycle path constraints are only valid if the logic use to sample the tl_cfg_ctl and tl_cfg_sts signals
# are as designed in the Altera provided files altpcierd_tl_cfg_sample.v and altpcierd_tl_cfg_sample.vhd
@@ -15,20 +15,20 @@ set_false_path -to {*|altera_pcie_serdes:serdes|*|rx_digitalreset_reg0c[0]}
# Hard IP block in Stratix IV, Arria II, Cyclone IV and HardCopy IV devices.
# These constraints are not neccesary for PCI Express Hard IP in Stratix V devices.
#
-global tl_cfg_ctl_wr_setup
-global tl_cfg_sts_wr_setup
+#global tl_cfg_ctl_wr_setup
+#global tl_cfg_sts_wr_setup
#
# If there are consistent hold time violations for the tl_cfg_ctl_wr signal in your chosen device and design,
# the multicycle setup constraint for tl_cfg_ctl_wr can be changed from 1 to 0 in the following variable:
-set tl_cfg_ctl_wr_setup 1
+#set tl_cfg_ctl_wr_setup 1
#
# If there are consistent hold time violations for the tl_cfg_sts_wr signal in your chosen device and design,
# the multicycle setup constraint for tl_cfg_sts_wr can be changed from 1 to 0 in the following variable:
-set tl_cfg_sts_wr_setup 1
+#set tl_cfg_sts_wr_setup 1
#
#set_multicycle_path -start -setup -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_ctl_wr}] $tl_cfg_ctl_wr_setup
-set_multicycle_path -end -setup -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_ctl[*]}] [expr $tl_cfg_ctl_wr_setup + 2]
-set_multicycle_path -end -hold -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_ctl[*]}] 3
+#set_multicycle_path -end -setup -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_ctl[*]}] [expr $tl_cfg_ctl_wr_setup + 2]
+#set_multicycle_path -end -hold -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_ctl[*]}] 3
#
#set_multicycle_path -start -setup -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_sts_wr}] $tl_cfg_sts_wr_setup
#set_multicycle_path -end -setup -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_sts[*]}] [expr $tl_cfg_sts_wr_setup + 2]
--
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