From 1e91b2391bf4ce6a58d8ae10c4b9308c950b2f0a Mon Sep 17 00:00:00 2001
From: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
Date: Wed, 13 Dec 2017 14:06:53 +0100
Subject: [PATCH] no technical change, cleanup copyright holders

---
 modules/common/gc_delay_line.vhd              | 28 +++++++++++++++++
 modules/common/gc_frequency_meter.vhd         | 29 +++++++++++++++++
 modules/common/gc_prio_encoder.vhd            | 28 +++++++++++++++++
 modules/common/gc_reset.vhd                   | 28 +++++++++++++++++
 modules/common/gc_rr_arbiter.vhd              | 29 +++++++++++++++++
 modules/common/gc_single_reset_gen.vhd        |  1 +
 modules/common/gc_sync_register.vhd           | 27 ++++++++++++++++
 .../wb_async_bridge/wb_async_bridge.vhd       | 18 ++++++++++-
 .../wb_async_bridge/xwb_async_bridge.vhd      | 30 ++++++++++++++++++
 .../wishbone/wb_axi4lite_bridge/axi4_pkg.vhd  | 29 +++++++++++++++++
 .../wb_axi4lite_bridge/wb_axi4lite_bridge.vhd | 29 +++++++++++++++++
 .../xwb_axi4lite_bridge.vhd                   | 29 +++++++++++++++++
 modules/wishbone/wb_dpram/xwb_dpram.vhd       | 20 ++++++++++--
 .../wishbone/wb_gpio_port/wb_gpio_port.vhd    | 18 +++++++++--
 .../wishbone/wb_gpio_port/xwb_gpio_port.vhd   | 30 ++++++++++++++++++
 modules/wishbone/wb_simple_timer/wb_tics.vhd  | 20 ++++++++++--
 modules/wishbone/wb_simple_timer/xwb_tics.vhd | 30 ++++++++++++++++++
 .../wb_slave_adapter/wb_slave_adapter.vhd     | 31 +++++++++++++++++++
 modules/wishbone/wb_spi/wb_spi.vhd            | 28 +++++++++++++++++
 modules/wishbone/wb_spi/xwb_spi.vhd           | 28 +++++++++++++++++
 modules/wishbone/wb_uart/uart_async_rx.vhd    | 29 +++++++++++++++++
 modules/wishbone/wb_uart/uart_async_tx.vhd    | 29 +++++++++++++++++
 modules/wishbone/wb_uart/uart_baud_gen.vhd    | 29 +++++++++++++++++
 modules/wishbone/wb_uart/wb_simple_uart.vhd   | 16 ++++++++++
 modules/wishbone/wb_uart/xwb_simple_uart.vhd  | 16 ++++++++++
 modules/wishbone/wb_vic/wb_vic.vhd            | 18 ++++++++++-
 modules/wishbone/wb_vic/xwb_vic.vhd           | 18 ++++++++++-
 modules/wishbone/wbgen2/wbgen2_dpssram.vhd    | 29 +++++++++++++++++
 modules/wishbone/wbgen2/wbgen2_eic.vhd        | 29 +++++++++++++++++
 modules/wishbone/wbgen2/wbgen2_fifo_async.vhd | 29 +++++++++++++++++
 modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd  | 28 +++++++++++++++++
 modules/wishbone/wbgen2/wbgen2_pkg.vhd        | 29 +++++++++++++++++
 modules/wishbone/wishbone_pkg.vhd             | 28 +++++++++++++++++
 33 files changed, 828 insertions(+), 9 deletions(-)

diff --git a/modules/common/gc_delay_line.vhd b/modules/common/gc_delay_line.vhd
index b713433..65f3673 100644
--- a/modules/common/gc_delay_line.vhd
+++ b/modules/common/gc_delay_line.vhd
@@ -1,3 +1,31 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrized delay block
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : gc_delay_line.vhd
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/modules/common/gc_frequency_meter.vhd b/modules/common/gc_frequency_meter.vhd
index c0cf346..39b15af 100644
--- a/modules/common/gc_frequency_meter.vhd
+++ b/modules/common/gc_frequency_meter.vhd
@@ -1,3 +1,32 @@
+-------------------------------------------------------------------------------
+-- Title      : Frequency meter
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : gc_frequency_meter.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012-2015 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 
 use ieee.std_logic_1164.all;
diff --git a/modules/common/gc_prio_encoder.vhd b/modules/common/gc_prio_encoder.vhd
index bc517e8..d637bf2 100644
--- a/modules/common/gc_prio_encoder.vhd
+++ b/modules/common/gc_prio_encoder.vhd
@@ -1,3 +1,31 @@
+-------------------------------------------------------------------------------
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : gc_prio_encoder.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/modules/common/gc_reset.vhd b/modules/common/gc_reset.vhd
index 5f41930..e4fa0a4 100644
--- a/modules/common/gc_reset.vhd
+++ b/modules/common/gc_reset.vhd
@@ -1,3 +1,31 @@
+-------------------------------------------------------------------------------
+-- Title      : Reset synchronizer and generator
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : gc_reset.vhd
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
diff --git a/modules/common/gc_rr_arbiter.vhd b/modules/common/gc_rr_arbiter.vhd
index 1ead771..0e060d4 100644
--- a/modules/common/gc_rr_arbiter.vhd
+++ b/modules/common/gc_rr_arbiter.vhd
@@ -1,3 +1,32 @@
+-------------------------------------------------------------------------------
+-- Title      : Round-robin arbiter
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : gc_rr_arbiter.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/modules/common/gc_single_reset_gen.vhd b/modules/common/gc_single_reset_gen.vhd
index e6c8219..93f0cd0 100644
--- a/modules/common/gc_single_reset_gen.vhd
+++ b/modules/common/gc_single_reset_gen.vhd
@@ -34,6 +34,7 @@
 -- Public License along with this source; if not, download it
 -- from http://www.gnu.org/licenses/lgpl-2.1.html
 --
+-------------------------------------------------------------------------------
 
 library ieee;
 use ieee.STD_LOGIC_1164.all;
diff --git a/modules/common/gc_sync_register.vhd b/modules/common/gc_sync_register.vhd
index 6098afe..8d43ef4 100644
--- a/modules/common/gc_sync_register.vhd
+++ b/modules/common/gc_sync_register.vhd
@@ -1,3 +1,30 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrized synchronizer
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : gc_sync_register.vhd
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2014-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
 --------------------------------------------------------------------------------
 --  Modifications:
 --      2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
diff --git a/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd b/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
index a6841be..d5d0838 100644
--- a/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
+++ b/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
@@ -16,7 +16,23 @@
 -- TODO:
 -- - implement write queueing and read prefetching (for speed improvement)
 -------------------------------------------------------------------------------
--- Copyright (c) 2010 Tomasz Wlostowski
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description
diff --git a/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd b/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
index 15aef6f..2109a61 100644
--- a/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
+++ b/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
@@ -1,3 +1,33 @@
+------------------------------------------------------------------------------
+-- Title      : Atmel EBI asynchronous bus <-> Wishbone bridge
+-- Project    : White Rabbit Switch
+------------------------------------------------------------------------------
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-05-18
+-- Last update: 2011-09-23
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'87
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use work.wishbone_pkg.all;
diff --git a/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd b/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
index 366e6c8..31b8d35 100644
--- a/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
+++ b/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
@@ -1,3 +1,32 @@
+-------------------------------------------------------------------------------
+-- Title      : AXI4Lite-to-WB bridge package
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : axi4_pkg.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 
diff --git a/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd b/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
index 302fca2..adfe1b4 100644
--- a/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
+++ b/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
@@ -1,3 +1,32 @@
+-------------------------------------------------------------------------------
+-- Title      : AXI4Lite-to-WB bridge
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wb_axi4lite_bridge.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd b/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
index 2b733f7..4f94d8a 100644
--- a/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
+++ b/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
@@ -1,3 +1,32 @@
+-------------------------------------------------------------------------------
+-- Title      : AXI4Lite-to-WB bridge wrapper
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : xwb_axi4lite_bridge.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/modules/wishbone/wb_dpram/xwb_dpram.vhd b/modules/wishbone/wb_dpram/xwb_dpram.vhd
index ebc6f60..71c3f38 100644
--- a/modules/wishbone/wb_dpram/xwb_dpram.vhd
+++ b/modules/wishbone/wb_dpram/xwb_dpram.vhd
@@ -4,7 +4,7 @@
 -------------------------------------------------------------------------------
 -- File       : wrc_dpram.vhd
 -- Author     : Grzegorz Daniluk
--- Company    : Elproma, CERN
+-- Company    : CERN
 -- Created    : 2011-02-15
 -- Last update: 2017-02-03
 -- Platform   : FPGA-generics
@@ -14,7 +14,23 @@
 --
 -- Dual port RAM with wishbone interface
 -------------------------------------------------------------------------------
--- Copyright (c) 2011 Grzegorz Daniluk
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description
diff --git a/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd b/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
index 8dd9aec..5b67513 100644
--- a/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
+++ b/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
@@ -11,9 +11,23 @@
 -------------------------------------------------------------------------------
 -- Description: Bidirectional GPIO port of configurable width (1 to 256 bits).
 -------------------------------------------------------------------------------
--- Copyright (c) 2010, 2011 CERN
+-- Copyright (c) 2010 - 2017 CERN
 --
--- 
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description
diff --git a/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd b/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
index 725f4ef..aa33f56 100644
--- a/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
+++ b/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
@@ -1,3 +1,33 @@
+------------------------------------------------------------------------------
+-- Title      : Wishbone GPIO port wrapper
+-- Project    : General Core Collection (gencores) Library
+------------------------------------------------------------------------------
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-05-18
+-- Last update: 2017-10-11
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'87
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 - 2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 
diff --git a/modules/wishbone/wb_simple_timer/wb_tics.vhd b/modules/wishbone/wb_simple_timer/wb_tics.vhd
index df7fa42..9a95b78 100644
--- a/modules/wishbone/wb_simple_timer/wb_tics.vhd
+++ b/modules/wishbone/wb_simple_timer/wb_tics.vhd
@@ -4,7 +4,7 @@
 -------------------------------------------------------------------------------
 -- File       : wb_tics.vhd
 -- Author     : Grzegorz Daniluk
--- Company    : Elproma
+-- Company    : CERN
 -- Created    : 2011-04-03
 -- Last update: 2013-09-13
 -- Platform   : FPGA-generics
@@ -15,7 +15,23 @@
 -- takes 1 usec. It is used by ptp-noposix as a replace of gettimeofday()
 -- function.
 -------------------------------------------------------------------------------
--- Copyright (c) 2011 Grzegorz Daniluk
+-- Copyright (c) 2011-2013 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description
diff --git a/modules/wishbone/wb_simple_timer/xwb_tics.vhd b/modules/wishbone/wb_simple_timer/xwb_tics.vhd
index 0cf11fc..7a0c0d7 100644
--- a/modules/wishbone/wb_simple_timer/xwb_tics.vhd
+++ b/modules/wishbone/wb_simple_timer/xwb_tics.vhd
@@ -1,3 +1,33 @@
+-------------------------------------------------------------------------------
+-- Title      : WhiteRabbit PTP Core tics wrapper
+-- Project    : WhiteRabbit
+-------------------------------------------------------------------------------
+-- File       : xwb_tics.vhd
+-- Author     : Grzegorz Daniluk
+-- Company    : CERN
+-- Created    : 2011-04-03
+-- Last update: 2013-09-13
+-- Platform   : FPGA-generics
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2013 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
 -- todo: configurable interrupt, output compare, PWM?
 
 library ieee;
diff --git a/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd b/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
index 5625244..193fc3d 100644
--- a/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
+++ b/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
@@ -1,6 +1,37 @@
+-------------------------------------------------------------------------------
+-- Title      : Wishbone Slave Adapter
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wb_slave_adapter.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Description:
+--
 -- universal "adapter"
 -- pipelined <> classic
 -- word-aligned/byte-aligned address
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
 
 library ieee;
 use ieee.std_logic_1164.all;
diff --git a/modules/wishbone/wb_spi/wb_spi.vhd b/modules/wishbone/wb_spi/wb_spi.vhd
index 9743bd9..556a7f2 100644
--- a/modules/wishbone/wb_spi/wb_spi.vhd
+++ b/modules/wishbone/wb_spi/wb_spi.vhd
@@ -1,3 +1,31 @@
+-------------------------------------------------------------------------------
+-- Title      : Wishbone SPI Master
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wb_spi.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
 --------------------------------------------------------------------------------
 --  Modifications:
 --      2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
diff --git a/modules/wishbone/wb_spi/xwb_spi.vhd b/modules/wishbone/wb_spi/xwb_spi.vhd
index 4071a18..ab0f55f 100644
--- a/modules/wishbone/wb_spi/xwb_spi.vhd
+++ b/modules/wishbone/wb_spi/xwb_spi.vhd
@@ -1,3 +1,31 @@
+-------------------------------------------------------------------------------
+-- Title      : Wishbone SPI Master wrapper
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : xwb_spi.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
 --------------------------------------------------------------------------------
 --  Modifications:
 --      2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
diff --git a/modules/wishbone/wb_uart/uart_async_rx.vhd b/modules/wishbone/wb_uart/uart_async_rx.vhd
index 34857ad..cf0a906 100644
--- a/modules/wishbone/wb_uart/uart_async_rx.vhd
+++ b/modules/wishbone/wb_uart/uart_async_rx.vhd
@@ -1,3 +1,32 @@
+------------------------------------------------------------------------------
+-- Title      : Simple Wishbone UART - receiver
+-- Project    : General Cores Collection (gencores) library
+------------------------------------------------------------------------------
+-- File       : uart_async_rx.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/modules/wishbone/wb_uart/uart_async_tx.vhd b/modules/wishbone/wb_uart/uart_async_tx.vhd
index f5acc92..d0a743f 100644
--- a/modules/wishbone/wb_uart/uart_async_tx.vhd
+++ b/modules/wishbone/wb_uart/uart_async_tx.vhd
@@ -1,3 +1,32 @@
+------------------------------------------------------------------------------
+-- Title      : Simple Wishbone UART - tranmitter
+-- Project    : General Cores Collection (gencores) library
+------------------------------------------------------------------------------
+-- File       : uart_async_tx.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/modules/wishbone/wb_uart/uart_baud_gen.vhd b/modules/wishbone/wb_uart/uart_baud_gen.vhd
index 8ba66d7..a565c5c 100644
--- a/modules/wishbone/wb_uart/uart_baud_gen.vhd
+++ b/modules/wishbone/wb_uart/uart_baud_gen.vhd
@@ -1,3 +1,32 @@
+------------------------------------------------------------------------------
+-- Title      : Simple Wishbone UART - baud generator
+-- Project    : General Cores Collection (gencores) library
+------------------------------------------------------------------------------
+-- File       : uart_baud_gen.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/modules/wishbone/wb_uart/wb_simple_uart.vhd b/modules/wishbone/wb_uart/wb_simple_uart.vhd
index 117f3ab..75379bf 100644
--- a/modules/wishbone/wb_uart/wb_simple_uart.vhd
+++ b/modules/wishbone/wb_uart/wb_simple_uart.vhd
@@ -17,6 +17,22 @@
 --   vice versa).
 -------------------------------------------------------------------------------
 -- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description
diff --git a/modules/wishbone/wb_uart/xwb_simple_uart.vhd b/modules/wishbone/wb_uart/xwb_simple_uart.vhd
index 19f3267..5914773 100644
--- a/modules/wishbone/wb_uart/xwb_simple_uart.vhd
+++ b/modules/wishbone/wb_uart/xwb_simple_uart.vhd
@@ -17,6 +17,22 @@
 --   vice versa).
 -------------------------------------------------------------------------------
 -- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description
diff --git a/modules/wishbone/wb_vic/wb_vic.vhd b/modules/wishbone/wb_vic/wb_vic.vhd
index 28f46d7..b9667cc 100644
--- a/modules/wishbone/wb_vic/wb_vic.vhd
+++ b/modules/wishbone/wb_vic/wb_vic.vhd
@@ -21,7 +21,23 @@
 -- - interrupt is acknowledged by writing to EIC_EOIR register.
 -- - register layout: see wb_vic.wb for details.
 -------------------------------------------------------------------------------
--- Copyright (c) 2010 Tomasz Wlostowski
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description
diff --git a/modules/wishbone/wb_vic/xwb_vic.vhd b/modules/wishbone/wb_vic/xwb_vic.vhd
index 40ff90e..7e18448 100644
--- a/modules/wishbone/wb_vic/xwb_vic.vhd
+++ b/modules/wishbone/wb_vic/xwb_vic.vhd
@@ -21,7 +21,23 @@
 -- - interrupt is acknowledged by writing to EIC_EOIR register.
 -- - register layout: see wb_vic.wb for details.
 -------------------------------------------------------------------------------
--- Copyright (c) 2010 Tomasz Wlostowski
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description
diff --git a/modules/wishbone/wbgen2/wbgen2_dpssram.vhd b/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
index 45905ad..0212e8c 100644
--- a/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
+++ b/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
@@ -1,3 +1,32 @@
+-------------------------------------------------------------------------------
+-- Title      : WBGEN components
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wbgen2_dpssram.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 
diff --git a/modules/wishbone/wbgen2/wbgen2_eic.vhd b/modules/wishbone/wbgen2/wbgen2_eic.vhd
index cc57a28..7962e6b 100644
--- a/modules/wishbone/wbgen2/wbgen2_eic.vhd
+++ b/modules/wishbone/wbgen2/wbgen2_eic.vhd
@@ -1,3 +1,32 @@
+-------------------------------------------------------------------------------
+-- Title      : WBGEN components
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wbgen2_eic.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd b/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
index 3fda6af..9b32767 100644
--- a/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
+++ b/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
@@ -1,3 +1,32 @@
+-------------------------------------------------------------------------------
+-- Title      : WBGEN components
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wbgen2_fifo_async.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 
diff --git a/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd b/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
index 8b09850..8905cc9 100644
--- a/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
+++ b/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
@@ -1,3 +1,31 @@
+-------------------------------------------------------------------------------
+-- Title      : WBGEN components
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wbgen2_fifo_sync.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
 
 library ieee;
 use ieee.std_logic_1164.all;
diff --git a/modules/wishbone/wbgen2/wbgen2_pkg.vhd b/modules/wishbone/wbgen2/wbgen2_pkg.vhd
index 18dc0a4..aabce15 100644
--- a/modules/wishbone/wbgen2/wbgen2_pkg.vhd
+++ b/modules/wishbone/wbgen2/wbgen2_pkg.vhd
@@ -1,3 +1,32 @@
+-------------------------------------------------------------------------------
+-- Title      : WBGEN components
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wbgen2_pkg.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2012 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 
diff --git a/modules/wishbone/wishbone_pkg.vhd b/modules/wishbone/wishbone_pkg.vhd
index 72e05db..e71d9b3 100644
--- a/modules/wishbone/wishbone_pkg.vhd
+++ b/modules/wishbone/wishbone_pkg.vhd
@@ -1,3 +1,31 @@
+-------------------------------------------------------------------------------
+-- Title      : Wishbone package
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wishbone_pkg.vhd
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 
 use ieee.std_logic_1164.all;
-- 
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