diff --git a/modules/common/gc_delay_line.vhd b/modules/common/gc_delay_line.vhd
index b7134331fc3ec3c41c31626da78d75ab91ea1f98..65f36730a7ec9c6e43f3944582c27ed65c2db2a6 100644
--- a/modules/common/gc_delay_line.vhd
+++ b/modules/common/gc_delay_line.vhd
@@ -1,3 +1,31 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrized delay block
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : gc_delay_line.vhd
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/modules/common/gc_frequency_meter.vhd b/modules/common/gc_frequency_meter.vhd
index c0cf346533525da9ce7086fa74319b32e647f920..39b15afc7ef75805f52099c4d3130f46b3608eae 100644
--- a/modules/common/gc_frequency_meter.vhd
+++ b/modules/common/gc_frequency_meter.vhd
@@ -1,3 +1,32 @@
+-------------------------------------------------------------------------------
+-- Title      : Frequency meter
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : gc_frequency_meter.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012-2015 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 
 use ieee.std_logic_1164.all;
diff --git a/modules/common/gc_prio_encoder.vhd b/modules/common/gc_prio_encoder.vhd
index bc517e8f6fbbe7b0162e41d5769e98e42fbbb23b..d637bf27d45d543fbf761db019d4f4de5237354b 100644
--- a/modules/common/gc_prio_encoder.vhd
+++ b/modules/common/gc_prio_encoder.vhd
@@ -1,3 +1,31 @@
+-------------------------------------------------------------------------------
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : gc_prio_encoder.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/modules/common/gc_reset.vhd b/modules/common/gc_reset.vhd
index 5f41930cefb44e8b317a4e18eae17b13c8688a96..e4fa0a49363fb3a7986bc328c9a9f598d9920724 100644
--- a/modules/common/gc_reset.vhd
+++ b/modules/common/gc_reset.vhd
@@ -1,3 +1,31 @@
+-------------------------------------------------------------------------------
+-- Title      : Reset synchronizer and generator
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : gc_reset.vhd
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
diff --git a/modules/common/gc_rr_arbiter.vhd b/modules/common/gc_rr_arbiter.vhd
index 1ead771523981a8ce45bb3eb0f1ededbeb900eff..0e060d43c5670d0c38e7e287a8bdbd4196674f93 100644
--- a/modules/common/gc_rr_arbiter.vhd
+++ b/modules/common/gc_rr_arbiter.vhd
@@ -1,3 +1,32 @@
+-------------------------------------------------------------------------------
+-- Title      : Round-robin arbiter
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : gc_rr_arbiter.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/modules/common/gc_single_reset_gen.vhd b/modules/common/gc_single_reset_gen.vhd
index e6c82197ca73bf35a3c550e76ca6a514b240772b..93f0cd0ec4498d27327ffbaa6560d2a9ef34bfd3 100644
--- a/modules/common/gc_single_reset_gen.vhd
+++ b/modules/common/gc_single_reset_gen.vhd
@@ -34,6 +34,7 @@
 -- Public License along with this source; if not, download it
 -- from http://www.gnu.org/licenses/lgpl-2.1.html
 --
+-------------------------------------------------------------------------------
 
 library ieee;
 use ieee.STD_LOGIC_1164.all;
diff --git a/modules/common/gc_sync_register.vhd b/modules/common/gc_sync_register.vhd
index 6098afe8f464c6f915e7929f095213fb9f8488e4..8d43ef44390f0c4de7c50d03ad4a713d0ecf0c0f 100644
--- a/modules/common/gc_sync_register.vhd
+++ b/modules/common/gc_sync_register.vhd
@@ -1,3 +1,30 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrized synchronizer
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : gc_sync_register.vhd
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2014-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
 --------------------------------------------------------------------------------
 --  Modifications:
 --      2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
diff --git a/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd b/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
index a6841be911d5b700999951b3606ab512c3d65ee0..d5d08389ab0b9aa8151e24cc72fc4c9f8099018d 100644
--- a/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
+++ b/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
@@ -16,7 +16,23 @@
 -- TODO:
 -- - implement write queueing and read prefetching (for speed improvement)
 -------------------------------------------------------------------------------
--- Copyright (c) 2010 Tomasz Wlostowski
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description
diff --git a/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd b/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
index 15aef6f34fb430493bba2379a8fc6acabcff0c8f..2109a617ea1c93eba09ddbeacdda6798f6aef035 100644
--- a/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
+++ b/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
@@ -1,3 +1,33 @@
+------------------------------------------------------------------------------
+-- Title      : Atmel EBI asynchronous bus <-> Wishbone bridge
+-- Project    : White Rabbit Switch
+------------------------------------------------------------------------------
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-05-18
+-- Last update: 2011-09-23
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'87
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use work.wishbone_pkg.all;
diff --git a/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd b/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
index 366e6c8a5fce0aa5b9e08ea7e43aced0358e63bb..31b8d358b3e74f09de60ce985ed2563fe84c93ff 100644
--- a/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
+++ b/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
@@ -1,3 +1,32 @@
+-------------------------------------------------------------------------------
+-- Title      : AXI4Lite-to-WB bridge package
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : axi4_pkg.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 
diff --git a/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd b/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
index 302fca2a8dc7e6ddfc4940a4bb9fc44dcddbec86..adfe1b4b9dbaab2e3f079fe6a447792e8464f2a9 100644
--- a/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
+++ b/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
@@ -1,3 +1,32 @@
+-------------------------------------------------------------------------------
+-- Title      : AXI4Lite-to-WB bridge
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wb_axi4lite_bridge.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd b/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
index 2b733f7b468affee15276500d7f2f1bb0b038d16..4f94d8ac1c9f0c802134b559263c6b718d97bd2d 100644
--- a/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
+++ b/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
@@ -1,3 +1,32 @@
+-------------------------------------------------------------------------------
+-- Title      : AXI4Lite-to-WB bridge wrapper
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : xwb_axi4lite_bridge.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/modules/wishbone/wb_dpram/xwb_dpram.vhd b/modules/wishbone/wb_dpram/xwb_dpram.vhd
index ebc6f608cd84bbcacaadac171cf8b1ad3d1ca865..71c3f384037ee18ba40ea04fbd919ffeefd3e0f3 100644
--- a/modules/wishbone/wb_dpram/xwb_dpram.vhd
+++ b/modules/wishbone/wb_dpram/xwb_dpram.vhd
@@ -4,7 +4,7 @@
 -------------------------------------------------------------------------------
 -- File       : wrc_dpram.vhd
 -- Author     : Grzegorz Daniluk
--- Company    : Elproma, CERN
+-- Company    : CERN
 -- Created    : 2011-02-15
 -- Last update: 2017-02-03
 -- Platform   : FPGA-generics
@@ -14,7 +14,23 @@
 --
 -- Dual port RAM with wishbone interface
 -------------------------------------------------------------------------------
--- Copyright (c) 2011 Grzegorz Daniluk
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description
diff --git a/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd b/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
index 8dd9aec6b811d5ec509fc2f435b5c875e37193a0..5b675134d5f3f4868a1e5f9ae75061124a8fe459 100644
--- a/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
+++ b/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
@@ -11,9 +11,23 @@
 -------------------------------------------------------------------------------
 -- Description: Bidirectional GPIO port of configurable width (1 to 256 bits).
 -------------------------------------------------------------------------------
--- Copyright (c) 2010, 2011 CERN
+-- Copyright (c) 2010 - 2017 CERN
 --
--- 
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description
diff --git a/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd b/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
index 725f4ef0a21ff2610b83d68bd3cb2c5ef54a104f..aa33f56ba7a3669293d01d3f071dde1e3a52a912 100644
--- a/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
+++ b/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
@@ -1,3 +1,33 @@
+------------------------------------------------------------------------------
+-- Title      : Wishbone GPIO port wrapper
+-- Project    : General Core Collection (gencores) Library
+------------------------------------------------------------------------------
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-05-18
+-- Last update: 2017-10-11
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'87
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 - 2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 
diff --git a/modules/wishbone/wb_simple_timer/wb_tics.vhd b/modules/wishbone/wb_simple_timer/wb_tics.vhd
index df7fa425081a7bde75349530b24c0c75b6676fac..9a95b787f82e07562585534e548c002a7f5f5c78 100644
--- a/modules/wishbone/wb_simple_timer/wb_tics.vhd
+++ b/modules/wishbone/wb_simple_timer/wb_tics.vhd
@@ -4,7 +4,7 @@
 -------------------------------------------------------------------------------
 -- File       : wb_tics.vhd
 -- Author     : Grzegorz Daniluk
--- Company    : Elproma
+-- Company    : CERN
 -- Created    : 2011-04-03
 -- Last update: 2013-09-13
 -- Platform   : FPGA-generics
@@ -15,7 +15,23 @@
 -- takes 1 usec. It is used by ptp-noposix as a replace of gettimeofday()
 -- function.
 -------------------------------------------------------------------------------
--- Copyright (c) 2011 Grzegorz Daniluk
+-- Copyright (c) 2011-2013 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description
diff --git a/modules/wishbone/wb_simple_timer/xwb_tics.vhd b/modules/wishbone/wb_simple_timer/xwb_tics.vhd
index 0cf11fc05d5223eb63f350a03f198ac18abb41f8..7a0c0d7a4989e8faabf438c68b5bbd894399a94a 100644
--- a/modules/wishbone/wb_simple_timer/xwb_tics.vhd
+++ b/modules/wishbone/wb_simple_timer/xwb_tics.vhd
@@ -1,3 +1,33 @@
+-------------------------------------------------------------------------------
+-- Title      : WhiteRabbit PTP Core tics wrapper
+-- Project    : WhiteRabbit
+-------------------------------------------------------------------------------
+-- File       : xwb_tics.vhd
+-- Author     : Grzegorz Daniluk
+-- Company    : CERN
+-- Created    : 2011-04-03
+-- Last update: 2013-09-13
+-- Platform   : FPGA-generics
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2013 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
 -- todo: configurable interrupt, output compare, PWM?
 
 library ieee;
diff --git a/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd b/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
index 56252448c05d956286fc4488ceaf07b2d041e6ad..193fc3dc31e00f5da73745cf6792ffcf9df63c85 100644
--- a/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
+++ b/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
@@ -1,6 +1,37 @@
+-------------------------------------------------------------------------------
+-- Title      : Wishbone Slave Adapter
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wb_slave_adapter.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Description:
+--
 -- universal "adapter"
 -- pipelined <> classic
 -- word-aligned/byte-aligned address
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
 
 library ieee;
 use ieee.std_logic_1164.all;
diff --git a/modules/wishbone/wb_spi/wb_spi.vhd b/modules/wishbone/wb_spi/wb_spi.vhd
index 9743bd9e3190cfab33dce2910c04a51c2633dbcf..556a7f216c902efce72dc0119c36bd0a1d59a629 100644
--- a/modules/wishbone/wb_spi/wb_spi.vhd
+++ b/modules/wishbone/wb_spi/wb_spi.vhd
@@ -1,3 +1,31 @@
+-------------------------------------------------------------------------------
+-- Title      : Wishbone SPI Master
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wb_spi.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
 --------------------------------------------------------------------------------
 --  Modifications:
 --      2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
diff --git a/modules/wishbone/wb_spi/xwb_spi.vhd b/modules/wishbone/wb_spi/xwb_spi.vhd
index 4071a1825c8d4b2ebdf70a2b6645bc757c6cb696..ab0f55fd95d028e88bc7e2588a3a7fe9fc2d54e2 100644
--- a/modules/wishbone/wb_spi/xwb_spi.vhd
+++ b/modules/wishbone/wb_spi/xwb_spi.vhd
@@ -1,3 +1,31 @@
+-------------------------------------------------------------------------------
+-- Title      : Wishbone SPI Master wrapper
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : xwb_spi.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
 --------------------------------------------------------------------------------
 --  Modifications:
 --      2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
diff --git a/modules/wishbone/wb_uart/uart_async_rx.vhd b/modules/wishbone/wb_uart/uart_async_rx.vhd
index 34857ad6591508afe8bd5cabd4c66cdfdf4c8398..cf0a906ca03c03e7c91a5b6ebaf9c02cf8401078 100644
--- a/modules/wishbone/wb_uart/uart_async_rx.vhd
+++ b/modules/wishbone/wb_uart/uart_async_rx.vhd
@@ -1,3 +1,32 @@
+------------------------------------------------------------------------------
+-- Title      : Simple Wishbone UART - receiver
+-- Project    : General Cores Collection (gencores) library
+------------------------------------------------------------------------------
+-- File       : uart_async_rx.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/modules/wishbone/wb_uart/uart_async_tx.vhd b/modules/wishbone/wb_uart/uart_async_tx.vhd
index f5acc92bd4042b4cff2f5b618a9e1a0e40a45e80..d0a743f397cb202ce5b7877abe4f6f3a70c29677 100644
--- a/modules/wishbone/wb_uart/uart_async_tx.vhd
+++ b/modules/wishbone/wb_uart/uart_async_tx.vhd
@@ -1,3 +1,32 @@
+------------------------------------------------------------------------------
+-- Title      : Simple Wishbone UART - tranmitter
+-- Project    : General Cores Collection (gencores) library
+------------------------------------------------------------------------------
+-- File       : uart_async_tx.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/modules/wishbone/wb_uart/uart_baud_gen.vhd b/modules/wishbone/wb_uart/uart_baud_gen.vhd
index 8ba66d7f9c943fbb3fa6fd1a66a2f1fe9d899ac3..a565c5c20cdeab080e1370baecdac50bb3d975b2 100644
--- a/modules/wishbone/wb_uart/uart_baud_gen.vhd
+++ b/modules/wishbone/wb_uart/uart_baud_gen.vhd
@@ -1,3 +1,32 @@
+------------------------------------------------------------------------------
+-- Title      : Simple Wishbone UART - baud generator
+-- Project    : General Cores Collection (gencores) library
+------------------------------------------------------------------------------
+-- File       : uart_baud_gen.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/modules/wishbone/wb_uart/wb_simple_uart.vhd b/modules/wishbone/wb_uart/wb_simple_uart.vhd
index 117f3ab942f0154f7428a36cb772499c935ff840..75379bf69babc412bd57d7d388543f07a353f86e 100644
--- a/modules/wishbone/wb_uart/wb_simple_uart.vhd
+++ b/modules/wishbone/wb_uart/wb_simple_uart.vhd
@@ -17,6 +17,22 @@
 --   vice versa).
 -------------------------------------------------------------------------------
 -- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description
diff --git a/modules/wishbone/wb_uart/xwb_simple_uart.vhd b/modules/wishbone/wb_uart/xwb_simple_uart.vhd
index 19f3267656ecdb85fe684c386b262752c5711cc2..5914773d2df85ad2c0ce2b66672dc4542a97ca19 100644
--- a/modules/wishbone/wb_uart/xwb_simple_uart.vhd
+++ b/modules/wishbone/wb_uart/xwb_simple_uart.vhd
@@ -17,6 +17,22 @@
 --   vice versa).
 -------------------------------------------------------------------------------
 -- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description
diff --git a/modules/wishbone/wb_vic/wb_vic.vhd b/modules/wishbone/wb_vic/wb_vic.vhd
index 28f46d71f0bbbb23a3e9d347811b5b2040a3f7fe..b9667cc716010141f67e6fe3ef6fbd85c2bb04f9 100644
--- a/modules/wishbone/wb_vic/wb_vic.vhd
+++ b/modules/wishbone/wb_vic/wb_vic.vhd
@@ -21,7 +21,23 @@
 -- - interrupt is acknowledged by writing to EIC_EOIR register.
 -- - register layout: see wb_vic.wb for details.
 -------------------------------------------------------------------------------
--- Copyright (c) 2010 Tomasz Wlostowski
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description
diff --git a/modules/wishbone/wb_vic/xwb_vic.vhd b/modules/wishbone/wb_vic/xwb_vic.vhd
index 40ff90e7522b8ef83780a1ec0a6fb0ecc1bc51e0..7e18448f2278329552eebefe651ac6d103a9b931 100644
--- a/modules/wishbone/wb_vic/xwb_vic.vhd
+++ b/modules/wishbone/wb_vic/xwb_vic.vhd
@@ -21,7 +21,23 @@
 -- - interrupt is acknowledged by writing to EIC_EOIR register.
 -- - register layout: see wb_vic.wb for details.
 -------------------------------------------------------------------------------
--- Copyright (c) 2010 Tomasz Wlostowski
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description
diff --git a/modules/wishbone/wbgen2/wbgen2_dpssram.vhd b/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
index 45905ad1978394cd19fdb1067280aa23900be059..0212e8c9fafe71241509d0f4e6260000555d0ab2 100644
--- a/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
+++ b/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
@@ -1,3 +1,32 @@
+-------------------------------------------------------------------------------
+-- Title      : WBGEN components
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wbgen2_dpssram.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 
diff --git a/modules/wishbone/wbgen2/wbgen2_eic.vhd b/modules/wishbone/wbgen2/wbgen2_eic.vhd
index cc57a28fc8f3de6113a9d5c72b7ace55004f5107..7962e6b6fc003cb7d0224ae3fb3a6cfc90410d01 100644
--- a/modules/wishbone/wbgen2/wbgen2_eic.vhd
+++ b/modules/wishbone/wbgen2/wbgen2_eic.vhd
@@ -1,3 +1,32 @@
+-------------------------------------------------------------------------------
+-- Title      : WBGEN components
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wbgen2_eic.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
diff --git a/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd b/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
index 3fda6af68f1bd5db8a1e7102e9bded7c98b0d368..9b32767a38039e941683a37eb3f10e9f7a6e1112 100644
--- a/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
+++ b/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
@@ -1,3 +1,32 @@
+-------------------------------------------------------------------------------
+-- Title      : WBGEN components
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wbgen2_fifo_async.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 
diff --git a/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd b/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
index 8b0985068bb574011df6741729dea378954dd537..8905cc9dcfec942a09dd4c5102b965f2440a842a 100644
--- a/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
+++ b/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
@@ -1,3 +1,31 @@
+-------------------------------------------------------------------------------
+-- Title      : WBGEN components
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wbgen2_fifo_sync.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
 
 library ieee;
 use ieee.std_logic_1164.all;
diff --git a/modules/wishbone/wbgen2/wbgen2_pkg.vhd b/modules/wishbone/wbgen2/wbgen2_pkg.vhd
index 18dc0a47b4ab595d832e81a3af4a507beef7f28c..aabce15a74d77cebf32ec102f28e1702c02fa02d 100644
--- a/modules/wishbone/wbgen2/wbgen2_pkg.vhd
+++ b/modules/wishbone/wbgen2/wbgen2_pkg.vhd
@@ -1,3 +1,32 @@
+-------------------------------------------------------------------------------
+-- Title      : WBGEN components
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wbgen2_pkg.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2012 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 
diff --git a/modules/wishbone/wishbone_pkg.vhd b/modules/wishbone/wishbone_pkg.vhd
index 72e05db47c09732230c2f260cf3bab0b1f65b59d..e71d9b3378fc9c99fbb07497207b44848f1e4512 100644
--- a/modules/wishbone/wishbone_pkg.vhd
+++ b/modules/wishbone/wishbone_pkg.vhd
@@ -1,3 +1,31 @@
+-------------------------------------------------------------------------------
+-- Title      : Wishbone package
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wishbone_pkg.vhd
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 
 use ieee.std_logic_1164.all;