diff --git a/modules/wishbone/Manifest.py b/modules/wishbone/Manifest.py
index 5ce69dee0879052b0e67670f7b8751e8422ace2b..db6b4079e7dbab3c5602427741be5140adb87e36 100644
--- a/modules/wishbone/Manifest.py
+++ b/modules/wishbone/Manifest.py
@@ -2,6 +2,7 @@ modules = { "local" :
[
# "wb_async_bridge",
+ "wb_onewire_master",
"wb_conmax",
"wb_gpio_port",
"wb_simple_timer",
diff --git a/modules/wishbone/wb_onewire_master/Manifest.py b/modules/wishbone/wb_onewire_master/Manifest.py
new file mode 100644
index 0000000000000000000000000000000000000000..6179509b59c7613e38d6fe4ffc4a6f188ff14855
--- /dev/null
+++ b/modules/wishbone/wb_onewire_master/Manifest.py
@@ -0,0 +1,2 @@
+files = ["wb_onewire_master.vhd",
+ "xwb_onewire_master.vhd"];
diff --git a/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd b/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d8e256450170a3e61207650d8fe40a836e81e881
--- /dev/null
+++ b/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
@@ -0,0 +1,88 @@
+library ieee;
+use ieee.STD_LOGIC_1164.all;
+
+use work.gencores_pkg.all;
+
+entity wb_onewire_master is
+
+ generic(
+ g_num_ports : integer := 1;
+ g_ow_btp_normal : string := "5.0";
+ g_ow_btp_overdrive : string := "1.0"
+ );
+
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_adr_i : in std_logic_vector(1 downto 0);
+ wb_dat_i : in std_logic_vector(31 downto 0);
+ wb_dat_o : out std_logic_vector(31 downto 0);
+ wb_ack_o : out std_logic;
+ wb_int_o: out std_logic;
+
+ owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
+ owr_en_o : out std_logic_vector(g_num_ports -1 downto 0);
+ owr_i : in std_logic_vector(g_num_ports -1 downto 0)
+ );
+
+end wb_onewire_master;
+
+
+architecture rtl of wb_onewire_master is
+
+ component sockit_owm
+ generic(
+ BTP_N : string;
+ BTP_O : string;
+ OWN : integer);
+
+ port(
+ clk : in std_logic;
+ rst : in std_logic;
+ bus_ren : in std_logic;
+ bus_wen : in std_logic;
+ bus_adr : in std_logic_vector(0 downto 0);
+ bus_wdt : in std_logic_vector(31 downto 0);
+ bus_rdt : out std_logic_vector(31 downto 0);
+ bus_irq : out std_logic;
+ owr_p : out std_logic_vector(OWN-1 downto 0);
+ owr_e : out std_logic_vector(OWN-1 downto 0);
+ owr_i : in std_logic_vector(OWN-1 downto 0)
+ );
+ end component;
+
+ signal bus_wen : std_logic;
+ signal bus_ren : std_logic;
+ signal rst : std_logic;
+begin -- rtl
+
+ bus_wen <= wb_cyc_i and wb_stb_i and wb_we_i;
+ bus_ren <= wb_cyc_i and wb_stb_i and not wb_we_i;
+
+ wb_ack_o <= wb_stb_i and wb_cyc_i;
+ rst <= not rst_n_i;
+
+ Wrapped_1wire : sockit_owm
+ generic map (
+ BTP_N => g_ow_btp_normal,
+ BTP_O => g_ow_btp_overdrive,
+ OWN => g_num_ports)
+ port map (
+ clk => clk_sys_i,
+ rst => rst,
+ bus_ren => bus_ren,
+ bus_wen => bus_wen,
+ bus_adr => wb_adr_i(0 downto 0),
+ bus_wdt => wb_dat_i,
+ bus_rdt => wb_dat_o,
+ bus_irq => wb_int_o,
+ owr_p => owr_pwren_o,
+ owr_e => owr_en_o,
+ owr_i => owr_i);
+end rtl;
+
diff --git a/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd b/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ff1fdc232977a43e9cb1af4e77514e5d8ad485d1
--- /dev/null
+++ b/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
@@ -0,0 +1,88 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.wishbone_pkg.all;
+
+entity xwb_onewire_master is
+ generic(
+ g_interface_mode : t_wishbone_interface_mode := CLASSIC;
+ g_num_ports : integer := 1;
+ g_ow_btp_normal : string := "5.0";
+ g_ow_btp_overdrive : string := "1.0"
+ );
+
+ port(
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+
+ -- Wishbone
+ slave_i : in t_wishbone_slave_in;
+ slave_o : out t_wishbone_slave_out;
+ desc_o : out t_wishbone_device_descriptor;
+
+ owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
+ owr_en_o : out std_logic_vector(g_num_ports -1 downto 0);
+ owr_i : in std_logic_vector(g_num_ports -1 downto 0)
+
+ );
+
+end xwb_onewire_master;
+
+architecture rtl of xwb_onewire_master is
+
+ component wb_onewire_master
+ generic (
+ g_num_ports : integer;
+ g_ow_btp_normal : string;
+ g_ow_btp_overdrive : string);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_i : in std_logic;
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_adr_i : in std_logic_vector(1 downto 0);
+ wb_dat_i : in std_logic_vector(31 downto 0);
+ wb_dat_o : out std_logic_vector(31 downto 0);
+ wb_ack_o : out std_logic;
+ wb_int_o : out std_logic;
+ owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
+ owr_en_o : out std_logic_vector(g_num_ports -1 downto 0);
+ owr_i : in std_logic_vector(g_num_ports -1 downto 0));
+ end component;
+
+begin -- rtl
+
+ gen_test_mode : if(g_interface_mode /= CLASSIC) generate
+
+ assert false report "xwb_onewire_master: this module can only work with CLASSIC wishbone interface" severity failure;
+
+ end generate gen_test_mode;
+
+ Wrapped_OW : wb_onewire_master
+ generic map (
+ g_num_ports => g_num_ports,
+ g_ow_btp_normal => g_ow_btp_normal,
+ g_ow_btp_overdrive => g_ow_btp_overdrive)
+ port map (
+ clk_sys_i => clk_sys_i,
+ rst_n_i => rst_n_i,
+ wb_cyc_i => slave_i.Cyc,
+ wb_sel_i => slave_i.Sel,
+ wb_stb_i => slave_i.stb,
+ wb_we_i => slave_i.we,
+ wb_adr_i => slave_i.adr(0 downto 0),
+ wb_dat_i => slave_i.Dat,
+ wb_dat_o => slave_o.dat,
+ wb_ack_o => slave_o.ack,
+ wb_int_o => slave_o.int,
+ owr_pwren_o => owr_pwren_o,
+ owr_en_o => owr_en_o,
+ owr_i => owr_i);
+
+ slave_o.stall <= '0';
+ slave_o.err <= '0';
+ slave_o.rty <= '0';
+
+end rtl;