Unhandled CDCs in the GBT-FPGA AWB interface

Starting with this line, all signals are captures with the 40 MHz frame_clk_i, although launched in different other clock domains. Here are the details:

Signal name	Clock domain
mgt_rx_headerflag_s	MGT_RXWORDCLK_o
mgt_rx_header_locked_s	MGT_RXWORDCLK_o
gbtbank_gbtrx_ready_s	MGT_RXWORDCLK_o and frame_clk_i
s_tx_aligned	MGT_TXWORDCLK_o
s_tx_aligned_val	MGT_TXWORDCLK_o
s_link_ready	MGT_TXWORDCLK_o and MGT_RXWORDCLK_o

This is successfully resolved by Vivado in smaller designs, but causes timing troubles with the TFC Submaster design, and potentially makes timing closure harder in other heavy designs as well.

Of interest to @w.zabolotny_AT_elka.pw.edu.pl