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Updates from cbm

The problem was that for vectors of registers with length 1 were considered to be single registers
(it was the very old approach). The "force_vec" attribute was ignored.

For example in the "test" demo project, change of the block1.xml:
  <creg name="X2" stb="1" reps="1">
    <field name="B1" width="1" desc="Start the operation" trigger="1" />
    <field name="B2" width="1" desc="Start the operation" default="0" />
    <field name="B3" width="1" desc="Start the operation" trigger="1" />....
  </creg>

causes the following error in GHDL compilation:

ghdl -a -g --work=general_cores -C  --std=93c --ieee=standard general-cores/modules/wishbone/wb_register/xwb_register.vhd
ghdl -a -g --work=agwb -C  --std=93c --ieee=standard gen/agwb_pkg.vhd
ghdl -a -g --work=agwb -C  --std=93c --ieee=standard gen/MAIN_const_pkg.vhd
ghdl -a -g --work=agwb -C  --std=93c --ieee=standard gen/SYS1_pkg.vhd
ghdl -a -g --work=agwb -C  --std=93c --ieee=standard gen/SYS1.vhd
gen/SYS1.vhd:44:60:error: can't match function call with type array type "ut_x2_array"
  signal int_X2_o : ut_X2_array(g_X2_size - 1 downto 0) := to_X2(std_logic_vector(to_unsigned(0,3))); -- Hex value: 0x0
                                                           ^
gen/SYS1.vhd:122:21:error: can't match function call with type array type "ut_x2_array"
        int_X2_o <= to_X2(std_logic_vector(to_unsigned(0,3))); -- Hex value: 0x0
                    ^
ghdl:error: compilation error

Similarly introduction of the vector of registers with length 1  with strobe or ack in demo "test_ao" results in the similar error.

This modification fixes the above problems.

Added information about the new AGWB paper.

Added link to the description of variants in Wiki

Added the "aggregated inputs" functionality. Of course, because the ACK lines are outputs, and the register values are inputs, two records: in_regs and ack_regs_o are needed to add that functionality.

https://github.com/wzab/agwb/issues/62

Added the schema converters rng2rnc.sh and rng2dtd.sh

This simplifies using the same core in deisgns with and without variants.

Added attribute: is_top="1" in the AMAP XML file in the top level module (modification suggested by @wfjm )

Fixed the bug with incorrect calculation of the mask for AMAP XML and IPbus XML mask generation.

Replaced "node" node name in AMAP XML file with:
1. "module" for block definitions,
2. "block" for block instances,
3. "register" for registers,
4. "field" for bitfields.

The true value of force_vec field of the INTERNAL object in AGWB may
result only from the usage of the "reps" attribute.

The generated registers wil be in uppercase.

This reverts commit 6a41a74f.

The set_max_delay was improperly defined. the req_m0* registers are in domain master_clk, but are driven from slave_clk.

The problem (and hints for solution) delivered by @wfjm.