Commit da428291 authored by Adrian Weber's avatar Adrian Weber
Browse files

Trb5sc with CRI connectivity for e.g. the CBM RICH detector. Later used for...

Trb5sc with CRI connectivity for e.g. the CBM RICH detector. Later used for temperature/magneitc field monitoring access and additional TDC input into data stream (e.g. Laser trigger)
parent 730899e0
../../trb3/scripts/compile.pl
\ No newline at end of file
library ieee;
USE IEEE.std_logic_1164.ALL;
use ieee.numeric_std.all;
use work.trb_net_std.all;
use work.trb_net16_hub_func.all;
package config is
------------------------------------------------------------------------------
--Begin of design configuration
------------------------------------------------------------------------------
--set to 0 for backplane serdes, set to 1 for SFP serdes
constant SERDES_NUM : integer := 1;
--TDC settings
constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5
constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
constant NUM_TDC_CHANNELS : integer range 1 to 65 := 5; -- number of tdc channels per module
constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 2; --the nearest power of two, for convenience reasons
constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 0; --double edge type: 0, 1, 2, 3
-- 0: single edge only,
-- 1: same channel,
-- 2: alternating channels,
-- 3: same channel with stretcher
constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size
-- mode: 0, 1, 2, 3, 7
-- size: 32, 64, 96, 128, dyn
constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC
-- 0: Single fine time as the sum of the two transitions
-- 1: Double fine time, individual transitions
-- 13: Debug - fine time + (if 0x3ff full chain)
-- 14: Debug - single fine time and the ROM addresses for the two transitions
-- 15: Debug - complete carry chain dump
constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2
--Runs with 120 MHz instead of 100 MHz
constant USE_120_MHZ : integer := c_NO;
--Use sync mode, RX clock for all parts of the FPGA
constant USE_RXCLOCK : integer := c_NO;
--Address settings
constant INIT_ADDRESS : std_logic_vector := x"F570";
constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"81";
constant INCLUDE_UART : integer := c_YES; --300 slices
constant INCLUDE_SPI : integer := c_YES; --300 slices
constant INCLUDE_LCD : integer := c_NO; --800 slices
constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices
--input monitor and trigger generation logic
constant INCLUDE_CALIBRATION : integer := c_YES;
constant INCLUDE_TDC : integer := c_YES; -- IMPORTANT: TDC part into entity has to be commented in/out by hand
-- (no generic possible due to constraints naming)
constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; --400 slices @32->2
constant INCLUDE_STATISTICS : integer := c_YES; --1300 slices, 1 RAM @32
constant TRIG_GEN_INPUT_NUM : integer := 0;
constant TRIG_GEN_OUTPUT_NUM : integer := 0;
constant MONITOR_INPUT_NUM : integer := 32;
constant INCLUDE_GBE : integer := c_NO;
constant GEN_BUSY_OUTPUT : integer := c_NO;
constant TRIGGER_COIN_COUNT : integer := 1;
constant TRIGGER_PULSER_COUNT : integer := 2;
constant TRIGGER_RAND_PULSER : integer := 1;
constant TRIGGER_ADDON_COUNT : integer := 2;
constant PERIPH_TRIGGER_COUNT : integer := 0;
constant ADDON_LINE_COUNT : integer := 2;--44;
constant CTS_OUTPUT_MULTIPLEXERS : integer := 1;
constant INCLUDE_TIMESTAMP_GENERATOR : integer := c_NO;
constant INCLUDE_ETM : integer range c_NO to c_YES := c_YES;
type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET, ETM_CHOICE_M26);
constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MBS_VULOM;
--constant ETM_ID : std_logic_vector(7 downto 0);
constant cts_rdo_additional_ports : integer := INCLUDE_TDC + INCLUDE_TIMESTAMP_GENERATOR + INCLUDE_ETM; --for TDC
constant FPGA_SIZE : string := "85KUM";
------------------------------------------------------------------------------
-- Hub config
-----------------------------------------------------------------------------
constant INTERFACE_NUM : integer := 1;
constant MII_IS_UPLINK : hub_mii_config_t := (0, 0,1,0, 0,0,0,0, 0,0,0,0 ,0,0,0,0, 0);
constant MII_IS_DOWNLINK : hub_mii_config_t := (1, 1,0,0, 0,0,0,0, 0,0,0,0 ,0,0,0,0, 0);
constant MII_IS_UPLINK_ONLY : hub_mii_config_t := (0, 0,1,0, 0,0,0,0, 0,0,0,0 ,0,0,0,0, 0);
------------------------------------------------------------------------------
--End of design configuration
------------------------------------------------------------------------------
type data_t is array (0 to 1023) of std_logic_vector(7 downto 0);
constant LCD_DATA : data_t := (others => x"00");
------------------------------------------------------------------------------
--Select settings by configuration
------------------------------------------------------------------------------
type intlist_t is array(0 to 7) of integer;
type hw_info_t is array(0 to 7) of unsigned(31 downto 0);
constant HW_INFO_BASE : unsigned(31 downto 0) := x"A5000000";
constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0);
constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0);
--declare constants, filled in body
constant HARDWARE_INFO : std_logic_vector(31 downto 0);
constant CLOCK_FREQUENCY : integer;
constant MEDIA_FREQUENCY : integer;
constant INCLUDED_FEATURES : std_logic_vector(63 downto 0);
end;
package body config is
--compute correct configuration mode
constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE );
constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ);
constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ);
function etm_id_func return std_logic_vector is
variable res : unsigned(7 downto 0);
begin
res := x"00";
if INCLUDE_ETM=c_YES then
res := x"60";
res := res + TO_UNSIGNED(ETM_CHOICE_type'pos(ETM_CHOICE), 4);
end if;
return std_logic_vector(res);
end function;
constant ETM_ID : std_logic_vector(7 downto 0) := etm_id_func;
function generateIncludedFeatures return std_logic_vector is
variable t : std_logic_vector(63 downto 0);
begin
t := (others => '0');
t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1
t(7 downto 0) := std_logic_vector(to_unsigned(1,8));
t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4));
t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3));
t(15) := '1'; --TDC
t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2));
t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1));
t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
t(54 downto 54) := "0";--std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
return t;
end function;
constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;
end package body;
Familyname => 'ECP5UM',
Devicename => 'LFE5UM-85F',
Package => 'CABGA756',
Speedgrade => '8',
TOPNAME => "trb5sc_template",
lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
lm_license_file_for_par => "1702\@jspc29",
lattice_path => '/d/jspc29/lattice/diamond/3.10_x64',
synplify_path => '/d/jspc29/lattice/synplify/O-2018.09-SP1/',
nodelist_file => '../nodelist_frankfurt.txt',
pinout_file => 'trb5sc_tdc',
par_options => '../par.p2t',
#Include only necessary lpf files
include_TDC => 1,
include_GBE => 0,
#Report settings
firefox_open => 0,
twr_number_of_errors => 20,
no_ltxt2ptxt => 1, #if there is no serdes being used
Familyname => 'ECP5UM',
Devicename => 'LFE5UM-85F',
Package => 'CABGA756',
Speedgrade => '8',
TOPNAME => "trb5sc_cbmrich",
lm_license_file_for_synplify => "7788\@fb07pc-u102325",
lm_license_file_for_par => "7788\@fb07pc-u102325",
lattice_path => '/usr/local/diamond/3.11_x64/',
synplify_path => '/usr/local/diamond/3.11_x64/synpbase',
synplify_command => "synpwrap -fg -options",
#synplify_command => "ssh adrian\@jspc37.x-matter.uni-frankfurt.de \"cd /local/adrian/git/dirich/combiner_cts/; LM_LICENSE_FILE=27020\@jspc29 /d/jspc29/lattice/synplify/O-2018.09-SP1/bin/synplify_premier -batch combiner.prj\"",
nodelist_file => '../nodes_lxhadeb07.txt',
par_options => '../par.p2t',
#Include only necessary lpf files
pinout_file => 'trb5sc_tdc', #name of pin-out file, if not equal TOPNAME
include_TDC => 1,
include_GBE => 0,
#Report settings
firefox_open => 0,
twr_number_of_errors => 20,
no_ltxt2ptxt => 1, #if there is no serdes being used
<?xml version="1.0" encoding="UTF-8"?>
<DiamondModule name="FIFO_36x128" module="FIFO" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2021 01 13 11:55:23.226" version="5.1" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
<File name="FIFO_36x128.lpc" type="lpc" modified="2021 01 13 11:55:20.000"/>
<File name="FIFO_36x128.vhd" type="top_level_vhdl" modified="2021 01 13 11:55:20.000"/>
<File name="FIFO_36x128_tmpl.vhd" type="template_vhdl" modified="2021 01 13 11:55:20.000"/>
<File name="tb_FIFO_36x128_tmpl.vhd" type="testbench_vhdl" modified="2021 01 13 11:55:20.000"/>
</Package>
</DiamondModule>
[Device]
Family=ecp5um
PartType=LFE5UM-85F
PartName=LFE5UM-85F-8BG756C
SpeedGrade=8
Package=CABGA756
OperatingCondition=COM
Status=P
[IP]
VendorName=Lattice Semiconductor Corporation
CoreType=LPM
CoreStatus=Demo
CoreName=FIFO
CoreRevision=5.1
ModuleName=FIFO_36x128
SourceFormat=VHDL
ParameterFileVersion=1.0
Date=01/13/2021
Time=11:55:20
[Parameters]
Verilog=0
VHDL=1
EDIF=1
Destination=Synplicity
Expression=BusA(0 to 7)
Order=Big Endian [MSB:LSB]
IO=0
FIFOImp=EBR Based
Depth=128
Width=36
regout=0
CtrlByRdEn=0
EmpFlg=1
PeMode=Static - Dual Threshold
PeAssert=2
PeDeassert=4
FullFlg=1
PfMode=Static - Dual Threshold
PfAssert=126
PfDeassert=124
Reset=Async
Reset1=Sync
RDataCount=0
EnECC=0
EnFWFT=0
[Command]
cmd_line= -w -n FIFO_36x128 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 128 -width 36 -no_enable -pe 2 -pe2 4 -pf 126 -pf2 124 -reset_rel SYNC
This diff is collapsed.
<?xml version="1.0" encoding="UTF-8"?>
<DiamondModule name="FIFO_36x64" module="FIFO" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2021 01 13 11:49:53.862" version="5.1" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
<File name="FIFO_36x64.lpc" type="lpc" modified="2021 01 13 11:49:50.000"/>
<File name="FIFO_36x64.vhd" type="top_level_vhdl" modified="2021 01 13 11:49:50.000"/>
<File name="FIFO_36x64_tmpl.vhd" type="template_vhdl" modified="2021 01 13 11:49:50.000"/>
<File name="tb_FIFO_36x64_tmpl.vhd" type="testbench_vhdl" modified="2021 01 13 11:49:50.000"/>
</Package>
</DiamondModule>
[Device]
Family=ecp5um
PartType=LFE5UM-85F
PartName=LFE5UM-85F-8BG756C
SpeedGrade=8
Package=CABGA756
OperatingCondition=COM
Status=P
[IP]
VendorName=Lattice Semiconductor Corporation
CoreType=LPM
CoreStatus=Demo
CoreName=FIFO
CoreRevision=5.1
ModuleName=FIFO_36x64
SourceFormat=VHDL
ParameterFileVersion=1.0
Date=01/13/2021
Time=11:49:50
[Parameters]
Verilog=0
VHDL=1
EDIF=1
Destination=Synplicity
Expression=BusA(0 to 7)
Order=Big Endian [MSB:LSB]
IO=0
FIFOImp=EBR Based
Depth=64
Width=36
regout=0
CtrlByRdEn=0
EmpFlg=1
PeMode=Static - Dual Threshold
PeAssert=2
PeDeassert=4
FullFlg=1
PfMode=Static - Dual Threshold
PfAssert=62
PfDeassert=60
Reset=Async
Reset1=Sync
RDataCount=0
EnECC=0
EnFWFT=0
[Command]
cmd_line= -w -n FIFO_36x64 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ebfifo -sync_mode -depth 64 -width 36 -no_enable -pe 2 -pe2 4 -pf 62 -pf2 60 -reset_rel SYNC
This diff is collapsed.
<?xml version="1.0" encoding="UTF-8"?>
<DiamondModule name="RAM_pseudo_DP_wReg_36x1k" module="RAM_DP" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2021 01 13 11:56:03.338" version="6.5" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
<File name="" type="mem" modified="2021 01 13 11:56:03.000"/>
<File name="RAM_pseudo_DP_wReg_36x1k.lpc" type="lpc" modified="2021 01 13 11:56:00.000"/>
<File name="RAM_pseudo_DP_wReg_36x1k.vhd" type="top_level_vhdl" modified="2021 01 13 11:56:01.000"/>
<File name="RAM_pseudo_DP_wReg_36x1k_tmpl.vhd" type="template_vhdl" modified="2021 01 13 11:56:01.000"/>
<File name="tb_RAM_pseudo_DP_wReg_36x1k_tmpl.vhd" type="testbench_vhdl" modified="2021 01 13 11:56:01.000"/>
</Package>
</DiamondModule>
[Device]
Family=ecp5um
PartType=LFE5UM-85F
PartName=LFE5UM-85F-8BG756C
SpeedGrade=8
Package=CABGA756
OperatingCondition=COM
Status=P
[IP]
VendorName=Lattice Semiconductor Corporation
CoreType=LPM
CoreStatus=Demo
CoreName=RAM_DP
CoreRevision=6.5
ModuleName=RAM_pseudo_DP_wReg_36x1k
SourceFormat=VHDL
ParameterFileVersion=1.0
Date=01/13/2021
Time=11:56:00
[Parameters]
Verilog=0
VHDL=1
EDIF=1
Destination=Synplicity
Expression=BusA(0 to 7)
Order=Big Endian [MSB:LSB]
IO=0
RAddress=1024
RData=36
WAddress=1024
WData=36
enByte=0
ByteSize=9
OutputEn=1
ClockEn=0
Optimization=Speed
Reset=Sync
Reset1=Sync
Init=0
MemFile=
MemFormat=bin
EnECC=0
Pipeline=0
init_data=0
[FilesGenerated]
=mem
[Command]
cmd_line= -w -n RAM_pseudo_DP_wReg_36x1k -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type ramdps -device LFE5UM-85F -raddr_width 10 -rwidth 36 -waddr_width 10 -wwidth 36 -rnum_words 1024 -wnum_words 1024 -outdata REGISTERED -cascade -1 -resetmode SYNC -sync_reset -mem_init0
// nodes file for parallel place&route
[jspc37]
SYSTEM = linux
CORENUM = 7
ENV = /d/jspc29/lattice/310_settings.sh
WORKDIR = /d/jspc22/trb/git/trb5sc/template/workdir
[jspc57]
SYSTEM = linux
CORENUM = 3
ENV = /d/jspc29/lattice/310_settings.sh
WORKDIR = /d/jspc22/trb/git/trb5sc/template/workdir
-w
#-y
-l 5
#-m nodelist.txt # Controlled by the compile.pl script.
#-n 1 # Controlled by the compile.pl script.
-s 10
-t 11
-c 2
-e 2
-i 10
#-exp parPlcInLimit=0
#-exp parPlcInNeighborSize=1
#General PAR Command Line Options
# -w With this option, any files generated will overwrite existing files
# (e.g., any .par, .pad files).
# -y Adds the Delay Summary Report in the .par file and creates the delay
# file (in .dly format) at the end of the par run.
#
#PAR Placement Command Line Options
# -l Specifies the effort level of the design from 1 (simplest designs)
# to 5 (most complex designs).
# -m Multi-tasking option. Controlled by the compile.pl script.
# -n Sets the number of iterations performed at the effort level
# specified by the -l option. Controlled by the compile.pl script.
# -s Save the number of best results for this run.
# -t Start placement at the specified cost table. Default is 1.
#
#PAR Routing Command Line Options
# -c Run number of cost-based cleanup passes of the router.
# -e Run number of delay-based cleanup passes of the router on
# completely-routed designs only.
# -i Run a maximum number of passes, stopping earlier only if the routing
# goes to 100 percent completion and all constraints are met.
#
#PAR Explorer Command Line Options
# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is
# compatible with all Lattice FPGA device families; however, most
# benefit has been demonstrated with benchmarks targeted to ECP5,
# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families.
# parCDR Enable the congestion-driven router (CDR) algorithm.
# Congestion-driven options like parCDR and parCDP can improve
# performance given a design with multiple congestion “hotspots.” The
# Layer > Congestion option of the Design Planner Floorplan View can
# help visualize routing congestion. Large congested areas may prevent
# the options from finding a successful solution.
# CDR is compatible with all Lattice FPGA device families however most
# benefit has been demonstrated with benchmarks targeted to ECP5,
# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families.
# paruseNBR NBR Router or Negotiation-based routing option. Supports all
# FPGA device families except LatticeXP and MachXO.
# When turned on, an alternate routing engine from the traditional
# Rip-up-based routing selection (RBR) is used. This involves an
# iterative routing algorithm that routes connections to achieve
# minimum delay cost. It does so by computing the demand on each
# routing resource and applying cost values per node. It will
# complete when an optimal solution is arrived at or the number of
# iterations is reached.
# parPathBased Path-based placement option. Path-based timing driven
# placement will yield better performance and more
# predictable results in many cases.
# parHold Additional hold time correction option. This option
# forces the router to automatically insert extra wires to compensate for the
# hold time violation.
# parHoldLimit This option allows you to set a limit on the number of
# hold time violations to be processed by the auto hold time correction option
# parHold.
# parPlcInLimit Cannot find in the online help
# parPlcInNeighborSize Cannot find in the online help
-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1
../../tdc/releases/tdc_v2.3/
\ No newline at end of file
COMMERCIAL ;
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
BLOCK RD_DURING_WR_PATHS ;
#################################################################
# Basic Settings
#################################################################
FREQUENCY PORT CLK_200 200 MHz;
FREQUENCY PORT CLK_125 125 MHz;
FREQUENCY PORT CLK_EXT 200 MHz;
FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
# FREQUENCY NET "med_stat_debug[11]" 200 MHz;
FREQUENCY NET "med2int_0.clk_full" 200 MHz;
# FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz;
BLOCK PATH TO PORT "LED*";
BLOCK PATH TO PORT "PROGRAMN";
BLOCK PATH TO PORT "TEMP_LINE";
BLOCK PATH FROM PORT "TEMP_LINE";
BLOCK PATH TO PORT "TEST_LINE*";
#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns;
#MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns;
#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;
#MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;
MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns;
MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns;
GSR_NET NET "clear_i";
# LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ;
REGION "MEDIA" "R81C44D" 13 25;
LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ;
# implementation: "workdir"
impl -add workdir -type fpga
# device options
set_option -technology ECP5UM
set_option -part LFE5UM_85F
set_option -package BG756C
set_option -speed_grade -8
set_option -part_companion ""
# compilation/mapping options
set_option -default_enum_encoding sequential
set_option -symbolic_fsm_compiler 1
set_option -top_module "trb5sc_cbmrich"
set_option -resource_sharing false
# map options
set_option -frequency 120
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -retiming 1
set_option -pipe 1
set_option -forcegsr false
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
set_option -compiler_compatible true
set_option -multi_file_compilation_unit 1
set_option -max_parallel_jobs 3
#set_option -automatic_compile_point 1
#set_option -continue_on_error 1
set_option -resolve_multiple_driver 1
# simulation options
set_option -write_verilog 0
set_option -write_vhdl 1
# automatic place and route (vendor) options
set_option -write_apr_constraint 0
# set result format/file last
project -result_format "edif"
project -result_file "workdir/trb5sc_cbmrich.edf"
set_option log_file "workdir/trb5sc_project.srf"
#implementation attributes
set_option -vlog_std v2001
set_option -project_relative_includes 1
impl -active "workdir"
####################
add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd"
#Packages
add_file -vhdl -lib work "workdir/version.vhd"
add_file -vhdl -lib work "config.vhd"
add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"