Commit be0faab9 authored by Jan Michel's avatar Jan Michel
Browse files

update Mimosis Design with automatic setting of delay on inputs

parent d68151c3
../../trb3sc/scripts/compile.pl
\ No newline at end of file
library ieee;
USE IEEE.std_logic_1164.ALL;
use ieee.numeric_std.all;
use work.trb_net_std.all;
package config is
------------------------------------------------------------------------------
--Begin of design configuration
------------------------------------------------------------------------------
--set to 0 for backplane serdes, set to 1 for SFP serdes
constant SERDES_NUM : integer := 1;
--TDC settings
constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5
constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module
constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons
constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3
-- 0: single edge only,
-- 1: same channel,
-- 2: alternating channels,
-- 3: same channel with stretcher
constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size
-- mode: 0, 1, 2, 3, 7
-- size: 32, 64, 96, 128, dyn
constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC
-- 0: Single fine time as the sum of the two transitions
-- 1: Double fine time, individual transitions
-- 13: Debug - fine time + (if 0x3ff full chain)
-- 14: Debug - single fine time and the ROM addresses for the two transitions
-- 15: Debug - complete carry chain dump
constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2
--Runs with 120 MHz instead of 100 MHz
constant USE_120_MHZ : integer := c_NO;
--Use sync mode, RX clock for all parts of the FPGA
constant USE_RXCLOCK : integer := c_NO;
--Address settings
constant INIT_ADDRESS : std_logic_vector := x"F575";
constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"82";
constant INCLUDE_UART : integer := c_NO; --300 slices
constant INCLUDE_SPI : integer := c_NO; --300 slices
constant INCLUDE_LCD : integer := c_NO; --800 slices
constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices
--input monitor and trigger generation logic
constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; --400 slices @32->2
constant INCLUDE_STATISTICS : integer := c_NO; --1300 slices, 1 RAM @32
constant TRIG_GEN_INPUT_NUM : integer := 32;
constant TRIG_GEN_OUTPUT_NUM : integer := 4;
constant MONITOR_INPUT_NUM : integer := 32;
------------------------------------------------------------------------------
--End of design configuration
------------------------------------------------------------------------------
type data_t is array (0 to 1023) of std_logic_vector(7 downto 0);
constant LCD_DATA : data_t := (others => x"00");
------------------------------------------------------------------------------
--Select settings by configuration
------------------------------------------------------------------------------
type intlist_t is array(0 to 7) of integer;
type hw_info_t is array(0 to 7) of unsigned(31 downto 0);
constant HW_INFO_BASE : unsigned(31 downto 0) := x"A5000000";
constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0);
constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0);
--declare constants, filled in body
constant HARDWARE_INFO : std_logic_vector(31 downto 0);
constant CLOCK_FREQUENCY : integer;
constant MEDIA_FREQUENCY : integer;
constant INCLUDED_FEATURES : std_logic_vector(63 downto 0);
end;
package body config is
--compute correct configuration mode
constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE );
constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ);
constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ);
function generateIncludedFeatures return std_logic_vector is
variable t : std_logic_vector(63 downto 0);
begin
t := (others => '0');
t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1
t(7 downto 0) := std_logic_vector(to_unsigned(1,8));
t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4));
t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3));
t(15) := '1'; --TDC
t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2));
t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1));
t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
t(54 downto 54) := "0";--std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
return t;
end function;
constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;
end package body;
###==== Start Configuration
[Device]
Family=ecp5um
PartType=LFE5UM-85F
PartName=LFE5UM-85F-8BG756C
SpeedGrade=8
Package=CABGA756
OperatingCondition=COM
Status=P
[IP]
VendorName=Lattice Semiconductor Corporation
CoreType=LPM
CoreStatus=Demo
CoreName=DDR_GENERIC
CoreRevision=6.0
ModuleName=mimosis_inp
SourceFormat=vhdl
ParameterFileVersion=1.0
Date=06/03/2019
Time=14:45:56
[Parameters]
Verilog=0
VHDL=1
EDIF=1
Destination=Synplicity
Expression=BusA(0 to 7)
Order=Big Endian [MSB:LSB]
IO=0
mode=Receive
trioddr=0
io_type=LVDS
width=8
freq_in=160
bandwidth=2560
aligned=Edge-to-Edge
pre-configuration=DISABLED
mode2=Receive
trioddr2=0
io_type2=LVDS
freq_in2=160
gear=2:1
aligned2=Centered
width2=8
DataLane=By Lane
EnECLK=0
Interface=GDDRX1_RX.SCLK.Centered
Delay=Dynamic User Defined
DelVal=1
EnInEdge=
NumEdge=BOTH
EnDynamic=0
GenPll=0
Freq=
AFreq=
Reference=0
IOBUF=
ReceiverSync=0
EnDynamicAlign=
DynamicAlign=
MIPIFilter=0
enClkIBuf=0
ClkIBuf=LVDS
[Command]
cmd_line= -w -n mimosis_inp -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 8 -freq_in 160 -gear 2 -del 1 -dynamic_delay -data_lane
<!DOCTYPE mimosis_inp>
<lattice:project mode="SingleComponent">
<spirit:component>
<spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
<spirit:library>LEGACY</spirit:library>
<spirit:name>DDR_GENERIC</spirit:name>
<spirit:version>6.0</spirit:version>
<spirit:fileSets>
<spirit:fileset>
<spirit:name>Diamond_Simulation</spirit:name>
<spirit:group>simulation</spirit:group>
<spirit:file>
<spirit:name>./mimosis_inp.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileset>
<spirit:fileset>
<spirit:name>Diamond_Synthesis</spirit:name>
<spirit:group>synthesis</spirit:group>
<spirit:file>
<spirit:name>./mimosis_inp.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileset>
</spirit:fileSets>
<spirit:componentGenerators>
<spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
<spirit:name>Configuration</spirit:name>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>${sbp_path}/generate_core.tcl</spirit:generatorExe>
<spirit:group>CONFIG</spirit:group>
</spirit:componentGenerator>
<spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
<spirit:name>Generation</spirit:name>
<spirit:apiType>none</spirit:apiType>
<spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
<spirit:group>GENERATE</spirit:group>
</spirit:componentGenerator>
</spirit:componentGenerators>
<spirit:model>
<spirit:views/>
<spirit:ports/>
</spirit:model>
<spirit:vendorExtensions>
<lattice:device>LFE5UM-85F-8BG756C</lattice:device>
<lattice:synthesis>synplify</lattice:synthesis>
<lattice:date>2019-05-31.19:33:04</lattice:date>
<lattice:modified>2019-06-03.14:45:58</lattice:modified>
<lattice:diamond>3.10.3.144</lattice:diamond>
<lattice:language>VHDL</lattice:language>
<lattice:attributes>
<lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
<lattice:attribute lattice:name="BBox">false</lattice:attribute>
<lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
<lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
<lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
<lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
<lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
<lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
<lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
<lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
<lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
<lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
<lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
<lattice:attribute lattice:name="Migrate">false</lattice:attribute>
<lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
</lattice:attributes>
<lattice:elements/>
<lattice:lpc>
<lattice:lpcsection lattice:name="Device"/>
<lattice:lpcentry>
<lattice:lpckey>Family</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>OperatingCondition</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>Package</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">CABGA756</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>PartName</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG756C</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>PartType</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>SpeedGrade</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>Status</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcsection lattice:name="IP"/>
<lattice:lpcentry>
<lattice:lpckey>CoreName</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">DDR_GENERIC</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>CoreRevision</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">6.0</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>CoreStatus</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>CoreType</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>Date</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">06/03/2019</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>ModuleName</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">mimosis_inp</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>ParameterFileVersion</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>SourceFormat</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>Time</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">14:45:56</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>VendorName</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcsection lattice:name="Parameters"/>
<lattice:lpcentry>
<lattice:lpckey>AFreq</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>ClkIBuf</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>DataLane</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">By Lane</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>DelVal</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>Delay</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">Dynamic User Defined</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>Destination</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>DynamicAlign</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>EDIF</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>EnDynamic</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>EnDynamicAlign</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>EnECLK</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>EnInEdge</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>Expression</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>Freq</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>GenPll</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>IO</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>IOBUF</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>Interface</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">GDDRX1_RX.SCLK.Centered</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>MIPIFilter</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>NumEdge</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">BOTH</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>Order</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>ReceiverSync</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>Reference</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>VHDL</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>Verilog</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>aligned</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">Edge-to-Edge</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>aligned2</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">Centered</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>bandwidth</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">2560</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>enClkIBuf</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>freq_in</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">160</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>freq_in2</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">160</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>gear</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">2:1</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>io_type</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>io_type2</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>mode</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">Receive</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>mode2</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">Receive</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>pre-configuration</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>trioddr</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>trioddr2</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>width</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcentry>
<lattice:lpckey>width2</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
</lattice:lpcentry>
<lattice:lpcsection lattice:name="Command"/>
<lattice:lpcentry>
<lattice:lpckey>cmd_line</lattice:lpckey>
<lattice:lpcvalue lattice:resolve="constant">-w -n mimosis_inp -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 8 -freq_in 160 -gear 2 -del 1 -dynamic_delay -data_lane</lattice:lpcvalue>
</lattice:lpcentry>
</lattice:lpc>
<lattice:groups/>
</spirit:vendorExtensions>
</spirit:component>
<spirit:design>
<spirit:vendor>LATTICE</spirit:vendor>
<spirit:library>LOCAL</spirit:library>
<spirit:name>mimosis_inp</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances/>
<spirit:adHocConnections/>
</spirit:design>
</lattice:project>
-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.3.144
-- Module Version: 5.8
--/d/jspc29/lattice/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n mimosis_inp -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 8 -freq_in 160 -gear 2 -del 1 -dynamic_delay -data_lane -fdc /d/jspc22/trb/lattice/sio/mimosis_inp/mimosis_inp.fdc
-- Mon Jun 3 14:45:58 2019
library IEEE;
use IEEE.std_logic_1164.all;
library ecp5um;
use ecp5um.components.all;
entity mimosis_inp is
port (
clkin: in std_logic;
reset: in std_logic;
sclk: out std_logic;
data_cflag: out std_logic_vector(7 downto 0);
data_direction: in std_logic_vector(7 downto 0);
data_loadn: in std_logic_vector(7 downto 0);
data_move: in std_logic_vector(7 downto 0);
datain: in std_logic_vector(7 downto 0);
q: out std_logic_vector(15 downto 0));
end mimosis_inp;
architecture Structure of mimosis_inp is
-- internal signal declarations
signal buf_clkin: std_logic;
signal qb7: std_logic;
signal qa7: std_logic;
signal qb6: std_logic;
signal qa6: std_logic;
signal qb5: std_logic;
signal qa5: std_logic;
signal qb4: std_logic;
signal qa4: std_logic;
signal qb3: std_logic;
signal qa3: std_logic;
signal qb2: std_logic;
signal qa2: std_logic;
signal qb1: std_logic;
signal qa1: std_logic;
signal qb0: std_logic;
signal qa0: std_logic;
signal sclk_t: std_logic;
signal dataini_t7: std_logic;
signal dataini_t6: std_logic;
signal dataini_t5: std_logic;
signal dataini_t4: std_logic;
signal dataini_t3: std_logic;
signal dataini_t2: std_logic;
signal dataini_t1: std_logic;
signal dataini_t0: std_logic;
signal buf_dataini7: std_logic;
signal buf_dataini6: std_logic;
signal buf_dataini5: std_logic;
signal buf_dataini4: std_logic;
signal buf_dataini3: std_logic;
signal buf_dataini2: std_logic;
signal buf_dataini1: std_logic;
signal buf_dataini0: std_logic;
attribute IO_TYPE : string;
-- attribute IO_TYPE of Inst3_IB : label is "LVDS";
attribute IO_TYPE of Inst1_IB7 : label is "LVDS";
attribute IO_TYPE of Inst1_IB6 : label is "LVDS";
attribute IO_TYPE of Inst1_IB5 : label is "LVDS";
attribute IO_TYPE of Inst1_IB4 : label is "LVDS";
attribute IO_TYPE of Inst1_IB3 : label is "LVDS";
attribute IO_TYPE of Inst1_IB2 : label is "LVDS";
attribute IO_TYPE of Inst1_IB1 : label is "LVDS";
attribute IO_TYPE of Inst1_IB0 : label is "LVDS";
attribute syn_keep : boolean;
attribute NGD_DRC_MASK : integer;
attribute NGD_DRC_MASK of Structure : architecture is 1;
begin
-- component instantiation statements
-- Inst3_IB: IB
-- port map (I=>clkin, O=>buf_clkin);
buf_clkin <= clkin;
Inst2_IDDRX1F7: IDDRX1F
port map (D=>dataini_t7, SCLK=>sclk_t, RST=>reset, Q0=>qa7,
Q1=>qb7);
Inst2_IDDRX1F6: IDDRX1F
port map (D=>dataini_t6, SCLK=>sclk_t, RST=>reset, Q0=>qa6,
Q1=>qb6);
Inst2_IDDRX1F5: IDDRX1F
port map (D=>dataini_t5, SCLK=>sclk_t, RST=>reset, Q0=>qa5,
Q1=>qb5);