Commit 730899e0 authored by Jan Michel's avatar Jan Michel
Browse files

Update trb5sc with new Serdes files

parent 3e20360b
......@@ -33,3 +33,6 @@ old
config_compile.pl
._Real_._Math_.vhd
diamond
cores/serdes_sync_0
cores/pcs.vhd
archv
This diff is collapsed.
[Device]
Family=ecp5um
OperatingCondition=COM
Package=CABGA756
PartName=LFE5UM-85F-8BG756C
PartType=LFE5UM-85F
SpeedGrade=8
Status=P
[IP]
CoreName=PCS
CoreRevision=8.2
CoreStatus=Demo
CoreType=LPM
Date=10/17/2018
ModuleName=serdes_sync_0
ParameterFileVersion=1.0
SourceFormat=vhdl
Time=11:31:35
VendorName=Lattice Semiconductor Corporation
[Parameters]
;ACHARA=0 00H
;ACHARB=0 00H
;ACHARM=0 00H
;RXMCAENABLE=Disabled
CDRLOLACTION=Full Recalibration
CDRLOLRANGE=3
CDR_MAX_RATE=2
CDR_MULT=10X
CDR_REF_RATE=200.0000
CH_MODE=Rx and Tx
Destination=Synplicity
EDIF=1
Expression=BusA(0 to 7)
IO=0
IO_TYPE=G8B10B
LEQ=Disabled
LOOPBACK=Disabled
LOSPORT=Enabled
NUM_CHS=1
Order=Big Endian [MSB:LSB]
PPORT_RX_RDY=Enabled
PPORT_TX_RDY=Enabled
PROTOCOL=G8B10B
PWAIT_RX_RDY=3000
PWAIT_TX_RDY=3000
RCSRC=Disabled
REFCLK_RATE=200.0000
RSTSEQSEL=Enabled
RX8B10B=Enabled
RXCOMMAA=1100000100
RXCOMMAB=0011111000
RXCOMMAM=1111111100
RXCOUPLING=AC
RXCTC=Disabled
RXCTCBYTEN=0 00H
RXCTCBYTEN1=0 00H
RXCTCBYTEN2=0 00H
RXCTCBYTEN3=0 00H
RXCTCMATCHPATTERN=M4-S4
RXDIFFTERM=50 ohms
RXFIFO_ENABLE=Enabled
RXINVPOL=Non-invert
RXLDR=Off
RXLOSTHRESHOLD=0
RXLSM=Enabled
RXSC=K28P157
RXWA=Barrel Shift
RX_DATA_WIDTH=8/10-Bit
RX_FICLK_RATE=200.0000
RX_LINE_RATE=2.0000
RX_RATE_DIV=Full Rate
SCIPORT=Enabled
SOFTLOL=Enabled
TX8B10B=Enabled
TXAMPLITUDE=800
TXDEPOST=Disabled
TXDEPRE=Disabled
TXDIFFTERM=50 ohms
TXFIFO_ENABLE=Enabled
TXINVPOL=Non-invert
TXLDR=Off
TXPLLLOLTHRESHOLD=1
TXPLLMULT=10X
TX_DATA_WIDTH=8/10-Bit
TX_FICLK_RATE=200.0000
TX_LINE_RATE=2.0000
TX_MAX_RATE=2
TX_RATE_DIV=Full Rate
VHDL=1
Verilog=0
[FilesGenerated]
serdes_sync_0.pp=pp
serdes_sync_0.sym=sym
serdes_sync_0.tft=tft
serdes_sync_0.txt=pcs_module
[SYSTEMPNR]
LN0=DCU0_CH1
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......@@ -138,11 +138,22 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd"
#add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v"
#channel 1, SFP
add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd"
add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v"
#add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd"
#add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v"
##########################################
add_file -vhdl -lib work "../../dirich/cores/pcs.vhd"
#########################################
#channel 0, backplane
#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd"
#channel 1, SFP
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd"
##########################################
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd"
add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v"
#TrbNet Endpoint
add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
......
......@@ -138,11 +138,23 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd"
#add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v"
#channel 1, SFP
add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd"
add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v"
#add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd"
#add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v"
##########################################
add_file -vhdl -lib work "../../dirich/cores/pcs.vhd"
#########################################
#channel 0, backplane
#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd"
#channel 1, SFP
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd"
##########################################
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd"
add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v"
#TrbNet Endpoint
add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
......
......@@ -11,7 +11,7 @@ lattice_path => '/d/jspc29/lattice/diamond/3.10_x64',
synplify_path => '/d/jspc29/lattice/synplify/O-2018.09-SP1/',
nodelist_file => '../nodelist_frankfurt.txt',
pinout_file => 'trb5sc_pqdc',
pinout_file => 'trb5sc_tdc',
par_options => '../par.p2t',
......
......@@ -139,11 +139,22 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd"
#add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v"
#channel 1, SFP
add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd"
add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v"
#add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd"
#add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v"
##########################################
add_file -vhdl -lib work "../../dirich/cores/pcs.vhd"
#########################################
#channel 0, backplane
#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd"
#channel 1, SFP
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd"
##########################################
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd"
add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v"
#TrbNet Endpoint
add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
......
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