Commit 720f1ada authored by Jan Michel's avatar Jan Michel
Browse files

update with I2C

parent 37a2de5f
......@@ -2,6 +2,16 @@ COMMERCIAL ;
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
SYSCONFIG MCCLK_FREQ=38.8 CONFIG_IOVOLTAGE=3.3 ; #BACKGROUND_RECONFIG=ON
BANK 0 VCCIO 2.5 V;
BANK 1 VCCIO 2.5 V;
BANK 2 VCCIO 2.5 V;
BANK 3 VCCIO 2.5 V;
BANK 4 VCCIO 3.3 V;
BANK 6 VCCIO 2.5 V;
BANK 7 VCCIO 2.5 V;
BANK 8 VCCIO 3.3 V;
#################################################################
# Clock I/O
#################################################################
......@@ -9,11 +19,11 @@ LOCATE COMP "CLK_125" SITE "AD1"; #was "OSC_CORE_125"
LOCATE COMP "CLK_200" SITE "AD32"; #was "OSC_CORE_200"
LOCATE COMP "CLK_EXT" SITE "C28"; #was "EXT_CLOCK"
DEFINE PORT GROUP "CLK_group" "CLK*" ;
IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
IOBUF GROUP "CLK_group" IO_TYPE=LVDS DIFFRESISTOR=100;
LOCATE COMP "ENPIRION_CLOCK" SITE "AM31";
IOBUF PORT "ENPIRION_CLOCK" IO_TYPE=LVTTL33;
# LOCATE COMP "ENPIRION_CLOCK" SITE "AM31";
# IOBUF PORT "ENPIRION_CLOCK" IO_TYPE=LVTTL33;
#################################################################
# Trigger I/O
......@@ -21,13 +31,13 @@ IOBUF PORT "ENPIRION_CLOCK" IO_TYPE=LVTTL33;
LOCATE COMP "TRIG_IN_BACKPL" SITE "AD3";
LOCATE COMP "TRIG_IN_RJ45" SITE "AC2";
DEFINE PORT GROUP "TRIG_IN_group" "TRIG_IN*" ;
IOBUF GROUP "TRIG_IN_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
IOBUF GROUP "TRIG_IN_group" IO_TYPE=LVDS DIFFRESISTOR=100;
LOCATE COMP "SPARE_0" SITE "AC3";
LOCATE COMP "SPARE_1" SITE "AB1";
DEFINE PORT GROUP "SPARE_group" "SPARE*" ;
IOBUF GROUP "SPARE_group" IO_TYPE=LVDS25 ;
IOBUF GROUP "SPARE_group" IO_TYPE=LVDS ;
#################################################################
# SFP
......@@ -67,7 +77,7 @@ IOBUF GROUP "FE_GPIO_group" IO_TYPE=LVCMOS25 PULLMODE=UP;
LOCATE COMP "FE_CLK_1" SITE "C5";
LOCATE COMP "FE_CLK_2" SITE "P5";
DEFINE PORT GROUP "FE_CLK_group" "FE_CLK*" ;
IOBUF GROUP "FE_CLK_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
IOBUF GROUP "FE_CLK_group" IO_TYPE=LVDS DIFFRESISTOR=100;
# LOCATE COMP "FE_CLK_2_N" SITE "P4";
# LOCATE COMP "FE_CLK_1_N" SITE "D5";
......@@ -201,7 +211,7 @@ LOCATE COMP "FE_DIFF_61" SITE "AB7";
LOCATE COMP "FE_DIFF_62" SITE "AB5";
LOCATE COMP "FE_DIFF_63" SITE "AC7";
DEFINE PORT GROUP "FE_DIFF_group" "FE_DIFF*" ;
IOBUF GROUP "FE_DIFF_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
IOBUF GROUP "FE_DIFF_group" IO_TYPE=LVDS DIFFRESISTOR=100;
#################################################################
......@@ -215,7 +225,7 @@ IOBUF PORT "I2C_SCL" IO_TYPE=LVCMOS25 ;
IOBUF PORT "TMP_ALERT" IO_TYPE=LVCMOS25 ;
LOCATE COMP "REPROGRAM" SITE "AH1";
LOCATE COMP "PROGRAMN" SITE "AH1";
IOBUF PORT "PROGRAMN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ;
......@@ -223,12 +233,12 @@ LOCATE COMP "IN_SELECT_EXT_CLOCK" SITE "A16";
IOBUF PORT "IN_SELECT_EXT_CLOCK" IO_TYPE=LVCMOS25 ;
# LOCATE COMP "FLASH_HOLD" SITE "AL1";
LOCATE COMP "FLASH_HOLD" SITE "AL1";
LOCATE COMP "FLASH_MISO" SITE "AJ2";
LOCATE COMP "FLASH_MOSI" SITE "AK2";
LOCATE COMP "FLASH_NCS" SITE "AJ3";
LOCATE COMP "FLASH_SCLK" SITE "AJ1";
# LOCATE COMP "FLASH_WP" SITE "AM2";
LOCATE COMP "FLASH_WP" SITE "AM2";
DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
IOBUF GROUP "FLASH_group" IO_TYPE=LVTTL33 PULLMODE=NONE;
......@@ -270,16 +280,16 @@ IOBUF PORT "LED_7" IO_TYPE=LVCMOS25 ;
IOBUF PORT "LED_8" IO_TYPE=LVCMOS25 ;
LOCATE COMP "LED_CLOCK_GREEN" SITE "AK32";
LOCATE COMP "LED_CLOCK_RED" SITE "AJ32";
LOCATE COMP "LED_RJ_GREEN_0" SITE "AK32";
LOCATE COMP "LED_RJ_RED_0" SITE "AJ32";
LOCATE COMP "LED_EXT_CLOCK" SITE "AJ30";
LOCATE COMP "LED_TRIGGER_GREEN" SITE "AM30";
LOCATE COMP "LED_TRIGGER_RED" SITE "AL30";
IOBUF PORT "LED_CLOCK_GREEN" IO_TYPE=LVTTL33 ;
IOBUF PORT "LED_CLOCK_RED" IO_TYPE=LVTTL33 ;
IOBUF PORT "LED_EXT_CLOCK" IO_TYPE=LVTTL33 ;
IOBUF PORT "LED_TRIGGER_GREEN" IO_TYPE=LVTTL33 ;
IOBUF PORT "LED_TRIGGER_RED" IO_TYPE=LVTTL33 ;
LOCATE COMP "LED_RJ_GREEN_1" SITE "AM30";
LOCATE COMP "LED_RJ_RED_1" SITE "AL30";
IOBUF PORT "LED_RJ_GREEN_0" IO_TYPE=LVTTL33 ;
IOBUF PORT "LED_RJ_RED_0" IO_TYPE=LVTTL33 ;
IOBUF PORT "LED_EXT_CLOCK" IO_TYPE=LVTTL33 ;
IOBUF PORT "LED_RJ_GREEN_1" IO_TYPE=LVTTL33 ;
IOBUF PORT "LED_RJ_RED_1" IO_TYPE=LVTTL33 ;
#################################################################
# Test & Other IO
......
......@@ -12,12 +12,12 @@ package config is
--set to 0 for backplane serdes, set to 1 for SFP serdes
constant SERDES_NUM : integer := 0;
constant SERDES_NUM : integer := 1;
--TDC settings
constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5
constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module
constant NUM_TDC_CHANNELS : integer range 1 to 65 := 9; -- number of tdc channels per module
constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons
constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3
-- 0: single edge only,
......@@ -47,7 +47,7 @@ package config is
constant INIT_ADDRESS : std_logic_vector := x"F350";
constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"80";
constant INCLUDE_UART : integer := c_NO; --300 slices
constant INCLUDE_UART : integer := c_YES; --300 slices
constant INCLUDE_SPI : integer := c_YES; --300 slices
constant INCLUDE_LCD : integer := c_NO; --800 slices
constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices
......@@ -56,7 +56,7 @@ package config is
constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; --400 slices @32->2
constant INCLUDE_STATISTICS : integer := c_NO; --1300 slices, 1 RAM @32
constant TRIG_GEN_INPUT_NUM : integer := 32;
constant TRIG_GEN_OUTPUT_NUM : integer := 2;
constant TRIG_GEN_OUTPUT_NUM : integer := 4;
constant MONITOR_INPUT_NUM : integer := 32;
------------------------------------------------------------------------------
......
......@@ -4,14 +4,14 @@ Package => 'CABGA756',
Speedgrade => '8',
TOPNAME => "dirich",
TOPNAME => "trb5sc_template",
lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
lm_license_file_for_par => "1702\@jspc29",
lattice_path => '/d/jspc29/lattice/diamond/3.9_x64',
synplify_path => '/d/jspc29/lattice/synplify/K-2015.09/',
nodelist_file => '../nodelist_frankfurt.txt',
pinout_file => 'dirich2',
pinout_file => 'trb5sc_basic',
par_options => '../par.p2t',
......
......@@ -4,7 +4,7 @@
#-m nodelist.txt # Controlled by the compile.pl script.
#-n 1 # Controlled by the compile.pl script.
-s 10
-t 10
-t 11
-c 2
-e 2
-i 10
......
......@@ -7,15 +7,16 @@ BLOCK RD_DURING_WR_PATHS ;
# Basic Settings
#################################################################
FREQUENCY PORT CLOCK_IN 200 MHz;
FREQUENCY PORT CLOCK_CAL 200 MHz;
FREQUENCY PORT CLK_200 200 MHz;
FREQUENCY PORT CLK_125 125 MHz;
FREQUENCY PORT CLK_EXT 200 MHz;
FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
FREQUENCY NET "med_stat_debug[11]" 200 MHz;
# FREQUENCY NET "med_stat_debug[11]" 200 MHz;
FREQUENCY NET "med2int_0.clk_full" 200 MHz;
FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz;
# FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz;
BLOCK PATH TO PORT "LED*";
......
......@@ -132,8 +132,17 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd"
add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v"
add_file -vhdl -lib work "../../dirich/cores/serdes_sync_0.vhd"
#########################################
#channel 0, backplane
#add_file -vhdl -lib work "../../dirich/cores/serdes_sync_0.vhd"
#add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v"
#channel 1, SFP
add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd"
add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v"
##########################################
add_file -vhdl -lib work "../../dirich/cores/pcs.vhd"
#TrbNet Endpoint
......@@ -178,6 +187,12 @@ add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd"
add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd"
add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd"
add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd"
add_file -vhdl -lib work "tdc_release/tdc_components.vhd"
add_file -vhdl -lib work "tdc_release/bit_sync.vhd"
add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd"
......
......@@ -12,7 +12,7 @@ use work.med_sync_define.all;
entity trb5sc_template is
port(
CLK_200 : in std_logic; --Main Oscillator
CLK_200 : in std_logic;
CLK_125 : in std_logic;
CLK_EXT : in std_logic;
......@@ -47,7 +47,7 @@ entity trb5sc_template is
PROGRAMN : out std_logic;
--I2C
I2C_SDA : inout std_logic;
I2C_SCL : out std_logic;
I2C_SCL : inout std_logic;
TMP_ALERT : in std_logic;
--LED
......@@ -61,7 +61,7 @@ entity trb5sc_template is
--Other Connectors
TEST : inout std_logic_vector(14 downto 1);
HDR_IO : inout std_logic_vector(15 downto 0);
HDR_IO : inout std_logic_vector(15 downto 0)
);
......@@ -109,12 +109,13 @@ architecture arch of trb5sc_template is
signal flash_clk_i : std_logic;
signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0);
signal header_io_i : std_logic_vector(10 downto 1);
signal timer : TIMERS;
signal hdr_io : std_logic_vector(9 downto 0);
signal led_off : std_logic;
--TDC
signal hit_in_i : std_logic_vector(NUM_TDC_CHANNELS-1 downto 1);
signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0);
signal trigger_inputs_i : std_logic_vector(TRIG_GEN_INPUT_NUM-1 downto 0);
attribute syn_keep of GSR_N : signal is true;
......@@ -156,7 +157,7 @@ trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and no
THE_CAL_PLL : entity work.pll_in125_out33
port map(
CLKI => CLOCK_CAL,
CLKI => CLK_125,
CLKOP => clk_cal
);
......@@ -217,6 +218,7 @@ THE_CAL_PLL : entity work.pll_in125_out33
ADDRESS_MASK => x"FFFF",
BROADCAST_BITMASK => x"FF",
REGIO_INIT_ENDPOINT_ID => x"0001",
REGIO_USE_1WIRE_INTERFACE => c_I2C,
TIMING_TRIGGER_RAW => c_YES,
--Configure data handler
DATA_INTERFACE_NUMBER => 1,
......@@ -254,6 +256,8 @@ THE_CAL_PLL : entity work.pll_in125_out33
BUS_MASTER_ACTIVE => bus_master_active,
ONEWIRE_INOUT => open,
I2C_SCL => I2C_SCL,
I2C_SDA => I2C_SDA,
--Timing registers
TIMERS_OUT => timer
);
......@@ -310,14 +314,14 @@ THE_CAL_PLL : entity work.pll_in125_out33
SPI_MISO_IN => spi_miso,
SPI_CLK_OUT => spi_clk,
--Header
HEADER_IO => HDR_IO,
HEADER_IO => HDR_IO(9 downto 0),
ADDITIONAL_REG(0) => led_off,
--LCD
LCD_DATA_IN => (others => '0'),
--ADC
ADC_CS => ADC_CS,
ADC_MOSI => ADC_DIN,
ADC_MISO => ADC_DOUT,
ADC_CS => ADC_NCS,
ADC_MOSI => ADC_MOSI,
ADC_MISO => ADC_MISO,
ADC_CLK => ADC_SCLK,
--Trigger & Monitor
MONITOR_INPUTS => monitor_inputs_i,
......@@ -346,21 +350,15 @@ THE_CAL_PLL : entity work.pll_in125_out33
---------------------------------------------------------------------------
monitor_inputs_i <= FE_DIFF(MONITOR_INPUT_NUM-1 downto 0);
trigger_inputs_i <= FE_DIFF(TRIGGER_INPUT_NUM-1 downto 0);
trigger_inputs_i <= FE_DIFF(TRIG_GEN_INPUT_NUM-1 downto 0);
hit_in_i <= FE_DIFF(NUM_TDC_CHANNELS-2 downto 0);
---------------------------------------------------------------------------
-- LCD Data to display
---------------------------------------------------------------------------
lcd_data(15 downto 0) <= timer.network_address;
lcd_data(47 downto 16) <= timer.microsecond;
lcd_data(79 downto 48) <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32));
lcd_data(91 downto 80) <= timer.temperature;
lcd_data(95 downto 92) <= x"0";
lcd_data(159 downto 96) <= timer.uid;
lcd_data(191 downto 160) <= debug_tools;
lcd_data(511 downto 192) <= (others => '0');
assert DOUBLE_EDGE_TYPE /= 2 report "double edge in separate channels: connections missing" severity error;
HDR_IO(15 downto 10) <= (others => '0');
TEST(13 downto 1) <= (others => '0');
TEST(14) <= FLASH_NCS;
---------------------------------------------------------------------------
-- LED
---------------------------------------------------------------------------
......@@ -368,9 +366,11 @@ THE_CAL_PLL : entity work.pll_in125_out33
LED_SFP_GREEN <= not med2int(0).stat_op(9) or led_off;
LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) or led_off;
LED_SFP_YELLOW <= not med2int(0).stat_op(8) or led_off;
LED <= x"F0";
LED_RJ_GREEN <= FLASH_NCS & FLASH_NCS;
LED_RJ_RED <= "11";
LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK or led_off;
-------------------------------------------------------------------------------
-- TDC
-------------------------------------------------------------------------------
......@@ -383,9 +383,9 @@ THE_CAL_PLL : entity work.pll_in125_out33
SIMULATION => c_NO)
port map (
RESET => reset_i,
CLK_TDC => CLOCK_IN,
CLK_TDC => clk_full,
CLK_READOUT => clk_sys, -- Clock for the readout
REFERENCE_TIME => TRIG_IN, -- Reference time input
REFERENCE_TIME => trigger_in_i, -- Reference time input
HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals
HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC
-- Trigger signals from handler
......@@ -396,14 +396,9 @@ THE_CAL_PLL : entity work.pll_in125_out33
BUS_TX => bustdc_tx,
-- Dubug signals
INFO_IN => timer,
LOGIC_ANALYSER_OUT => logic_analyser_i
LOGIC_ANALYSER_OUT => open
);
-- For single edge measurements
gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
hit_in_i <= FE_DIFF(NUM_TDC_CHANNELS-2 downto 0);
end generate;
-------------------------------------------------------------------------------
-- No trigger/data endpoint included
......
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment