GitLab

fix of crashung readout in case of triggers not together with in the DLM (CALIBRATION; seen while no DLM transmitted.). Now in case of 0xD trigger, the last DLM message is written to CTS and the readout is finished.

small changes to fix data written to fifo in hub logic. Before, first word was written to rx fifo in hub logic twice.

DCA bridge to trbNet in a UDP/GBE like manner. Testbench added. Only write direction is tested in simulation.

This achieves a deterministic phase of the downlink TX data with respect
to the reference clock (and system/CBM clock).

Add TX phase aligner core from CERN HPTD project:

https://gitlab.cern.ch/HPTD/tx_phase_aligner

This achieves TX phase alignment to a reference clock by the method
described in:

E. Mendes, S. Baron, C. Soos, J. Troska and P. Novellini, "Achieving
Picosecond-Level Phase Stability in Timing Distribution Systems With
Xilinx Ultrascale Transceivers," in IEEE Transactions on Nuclear
Science, vol. 67, no. 3, pp. 473-481, March 2020, doi:
10.1109/TNS.2020.2968112.

git-subtree-dir: hub_test/src/tx_phase_aligner
git-subtree-split: e92a060f338e99de064f09df812c65363268221b

init commit of two entitys to handle the slowcontrol between agwb/wishbone of cri and trbnet. Entities are based on trbnet to pci bridge and only an untested shelf. To be implemented

fix for data_ready signal and resulting 50% data acceptance. additional signal init values and reset for state machine

new DLM to CTS entity. This entity substitutes the previously use MBS chain. A trigger is now generated from EACH DLM message. In case the DLM messag eis the same as in the DLM before, a subtrigger is counted up. A subtrigger is used to generate readouts inbetween microtimeslices. The DLM message itself indicates the microtimeslice index. Updates for higher stability and more features will follow. This is the first version of the entity.

This was forgotten during the original change to 2.4 Gbps. It likely
worked anyway, because the GT settings for 2.4 Gbps with 120 MHz are
similar to 2.0 Gbps with 100 MHz.

Currently requires the sync_fix branch of trbnet to achieve timing
closure.

This gets rid of the separate fabric clock input port and prevents
timing errors stemming from the separate clock sources.

This puts all downlinks and the uplink on the same MTP connectors again,
so that a single MTP pair can be used for all RICH links in mCBM 2021.

small fix for the filling of the end of data with 0xAAAA. Minor fixes in simulation top entity to get a full data transfer

inclusion of online tdc calibration in data sender. CTS calibration has to be adjusted when TDC is implemented