Commit d222109a authored by Adrian Weber's avatar Adrian Weber
Browse files

improvements in simulation of dca bridge. full send and receive seems to work as expected.

parent 7712af73
......@@ -900,7 +900,7 @@ Resolution = ns
UserTimeUnit = default
; Default run length
RunLength = 1600 ns
RunLength = 2500 ns
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 10000000
......@@ -2220,7 +2220,7 @@ Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 v
Project_File_3 = /home/adrian/trbvhdl/trbnet/trb_net_components.vhd
Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1611048635 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_4 = /home/adrian/trbvhdl/cri/src/cri_trbnet_dca_bridge.vhd
Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1614766307 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1614777556 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 0 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_5 = /home/adrian/trbvhdl/trbnet/lattice/ecp3/fifo/fifo_19x16.vhd
Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1587396761 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 16 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_6 = /home/adrian/trbvhdl/trbnet/basics/priority_arbiter.vhd
......@@ -2236,7 +2236,7 @@ Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0
Project_File_11 = /home/adrian/trbvhdl/cri/src/cri_trbnet_dca_bridge_handler.vhd
Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1614685372 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_12 = /home/adrian/trbvhdl/cri/src/agwb_handler_dca_sim.vhd
Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1614594725 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 6 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1614776821 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_13 = /home/adrian/trbvhdl/cri/src/DCA_cores/ecp3/fifo_2kx34x17_wcnt/fifo_2kx34x17_wcnt.vhd
Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1614244548 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_14 = /home/adrian/trbvhdl/trbnet/trb_net16_hub_func.vhd
......@@ -2246,7 +2246,7 @@ Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0
Project_File_16 = /home/adrian/trbvhdl/cri/src/DCA_cores/ecp3/fifo_64kx16x32_wcnt/fifo_64kx16x32_wcnt.vhd
Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1614599180 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_17 = /home/adrian/trbvhdl/cri/src/DCA_bridge_tb/DCA_bridge_tb.vhd
Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1614765840 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002
Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1614777179 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2002
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
......
......@@ -41,7 +41,16 @@ signal DCA_REPLY_READ_OUT : std_logic;
signal DCA_REPLY_DATAREADY_IN_2 : std_logic;
signal DCA_REPLY_DATA_IN_2 : std_logic_vector(15 downto 0);
signal DCA_REPLY_PACKET_NUM_IN_2 : std_logic_vector( 2 downto 0);
signal DCA_REPLY_READ_OUT_2 : std_logic;
signal DCA_REPLY_READ_OUT_2 : std_logic := '0';
signal INIT_DATAREADY_OUT : std_logic_vector(1 downto 0);
signal REPLY_DATAREADY_IN : std_logic_vector( 1 downto 0) := "00";
signal REPLY_DATA_IN : std_logic_vector(31 downto 0) := x"00000000";
signal REPLY_PACKET_NUM_IN : std_logic_vector( 5 downto 0) := "000000";
signal REPLY_READ_OUT : std_logic_vector (1 downto 0) := "00";
signal STAT_locked : std_logic;
begin
......@@ -63,11 +72,11 @@ begin
DCA_INIT_PACKET_NUM_OUT => DCA_INIT_PACKET_NUM_OUT,
DCA_INIT_READ_IN => DCA_INIT_READ_IN,--DCA_INIT_READ_IN_i,
DCA_REPLY_DATAREADY_IN => '0',
DCA_REPLY_DATA_IN => x"1234",
DCA_REPLY_PACKET_NUM_IN => "000",
DCA_REPLY_READ_OUT => open,
DCA_BUSY_IN => '0',
DCA_REPLY_DATAREADY_IN => DCA_REPLY_DATAREADY_IN,
DCA_REPLY_DATA_IN => DCA_REPLY_DATA_IN,
DCA_REPLY_PACKET_NUM_IN => DCA_REPLY_PACKET_NUM_IN,
DCA_REPLY_READ_OUT => DCA_REPLY_READ_OUT,
DCA_BUSY_IN => STAT_locked,
MAKE_RESET_OUT => open,
CFG_MAX_REPLY_SIZE_IN => x"FFFFFFFF",
......@@ -78,7 +87,8 @@ begin
THE_HUBLOGIC : entity work.trb_net16_hub_logic
generic map (
--media interfaces
POINT_NUMBER => 2
POINT_NUMBER => 2,
MII_IS_UPLINK_ONLY => (c_YES, c_NO, c_NO, c_NO, c_NO, c_NO, c_NO, c_NO, c_NO, c_NO, c_NO, c_NO, c_NO, c_NO, c_NO, c_NO, c_NO)
)
port map(
CLK => CLK,
......@@ -93,14 +103,14 @@ THE_HUBLOGIC : entity work.trb_net16_hub_logic
INIT_PACKET_NUM_IN(5 downto 3) => (others => '0'),
INIT_READ_OUT(0) => DCA_INIT_READ_IN,
INIT_READ_OUT(1) => DCA_INIT_READ_IN_2,
INIT_DATAREADY_OUT => open,
INIT_DATAREADY_OUT => INIT_DATAREADY_OUT,
INIT_DATA_OUT => open,
INIT_PACKET_NUM_OUT => open,
INIT_READ_IN => "10",
REPLY_DATAREADY_IN => (others => '0'),
REPLY_DATA_IN => (others => '0'),
REPLY_PACKET_NUM_IN => (others => '0'),
REPLY_READ_OUT => open,
REPLY_DATAREADY_IN => REPLY_DATAREADY_IN,
REPLY_DATA_IN => REPLY_DATA_IN,
REPLY_PACKET_NUM_IN => REPLY_PACKET_NUM_IN,
REPLY_READ_OUT => REPLY_READ_OUT,
REPLY_DATAREADY_OUT(0) => DCA_REPLY_DATAREADY_IN,
REPLY_DATAREADY_OUT(1) => DCA_REPLY_DATAREADY_IN_2,
REPLY_DATA_OUT(15 downto 0) => DCA_REPLY_DATA_IN,
......@@ -112,13 +122,13 @@ THE_HUBLOGIC : entity work.trb_net16_hub_logic
--Status ports (for debugging)
STAT => open,
STAT_locked => open,
STAT_locked => STAT_locked,
STAT_POINTS_locked => open,
STAT_TIMEOUT => open,
STAT_ERRORBITS => open,
STAT_ALL_ERRORBITS => open,
CTRL_TIMEOUT_TIME => x"FFFF",
CTRL_activepoints => x"00000001",
CTRL_activepoints => x"00000003",
CTRL_TIMER_TICK => "00"
);
......@@ -304,7 +314,8 @@ THE_HUBLOGIC : entity work.trb_net16_hub_logic
-- START POLL
wait for 200 ns;
wait for 250 ns;
wb_slave_in.adr <= x"0000_0003" ;
wb_slave_in.dat <= x"0000_0000" ;
wb_slave_in.stb <= '1' ;
......@@ -314,7 +325,7 @@ THE_HUBLOGIC : entity work.trb_net16_hub_logic
wb_slave_in.stb <= '0' ;
wb_slave_in.cyc <= '0' ;
--
wait for 200 ns;
wait for 475 ns;
wb_slave_in.adr <= x"0000_0003" ;
wb_slave_in.dat <= x"0000_0000" ;
wb_slave_in.stb <= '1' ;
......@@ -323,7 +334,194 @@ THE_HUBLOGIC : entity work.trb_net16_hub_logic
wait for 25 ns;
wb_slave_in.stb <= '0' ;
wb_slave_in.cyc <= '0' ;
wait for 100 ns;
--1
wb_slave_in.adr <= x"0000_0002" ;
wb_slave_in.dat <= x"0000_0000" ;
wb_slave_in.stb <= '1' ;
wb_slave_in.cyc <= '1' ;
wb_slave_in.we <= '0';
wait for 25 ns;
wb_slave_in.stb <= '0' ;
wb_slave_in.cyc <= '0' ;
wait for 50 ns;
--2
wb_slave_in.adr <= x"0000_0002" ;
wb_slave_in.dat <= x"0000_0000" ;
wb_slave_in.stb <= '1' ;
wb_slave_in.cyc <= '1' ;
wb_slave_in.we <= '0';
wait for 25 ns;
wb_slave_in.stb <= '0' ;
wb_slave_in.cyc <= '0' ;
wait for 50 ns;
--3
wb_slave_in.adr <= x"0000_0002" ;
wb_slave_in.dat <= x"0000_0000" ;
wb_slave_in.stb <= '1' ;
wb_slave_in.cyc <= '1' ;
wb_slave_in.we <= '0';
wait for 25 ns;
wb_slave_in.stb <= '0' ;
wb_slave_in.cyc <= '0' ;
wait for 50 ns;
--4
wb_slave_in.adr <= x"0000_0002" ;
wb_slave_in.dat <= x"0000_0000" ;
wb_slave_in.stb <= '1' ;
wb_slave_in.cyc <= '1' ;
wb_slave_in.we <= '0';
wait for 25 ns;
wb_slave_in.stb <= '0' ;
wb_slave_in.cyc <= '0' ;
wait for 50 ns;
--5
wb_slave_in.adr <= x"0000_0002" ;
wb_slave_in.dat <= x"0000_0000" ;
wb_slave_in.stb <= '1' ;
wb_slave_in.cyc <= '1' ;
wb_slave_in.we <= '0';
wait for 25 ns;
wb_slave_in.stb <= '0' ;
wb_slave_in.cyc <= '0' ;
wait for 50 ns;
--6
wb_slave_in.adr <= x"0000_0002" ;
wb_slave_in.dat <= x"0000_0000" ;
wb_slave_in.stb <= '1' ;
wb_slave_in.cyc <= '1' ;
wb_slave_in.we <= '0';
wait for 25 ns;
wb_slave_in.stb <= '0' ;
wb_slave_in.cyc <= '0' ;
wait for 50 ns;
--7
wb_slave_in.adr <= x"0000_0002" ;
wb_slave_in.dat <= x"0000_0000" ;
wb_slave_in.stb <= '1' ;
wb_slave_in.cyc <= '1' ;
wb_slave_in.we <= '0';
wait for 25 ns;
wb_slave_in.stb <= '0' ;
wb_slave_in.cyc <= '0' ;
wait for 50 ns;
--8
wb_slave_in.adr <= x"0000_0002" ;
wb_slave_in.dat <= x"0000_0000" ;
wb_slave_in.stb <= '1' ;
wb_slave_in.cyc <= '1' ;
wb_slave_in.we <= '0';
wait for 25 ns;
wb_slave_in.stb <= '0' ;
wb_slave_in.cyc <= '0' ;
wait for 50 ns;
wait for 800 ns;
end process;
proc_readReg_AnswerHub : process
begin
REPLY_DATAREADY_IN <= "00";
wait until INIT_DATAREADY_OUT(1) = '1';
REPLY_DATAREADY_IN(1) <= '0';
wait for 20 ns;
wait until INIT_DATAREADY_OUT(1) = '0';
wait for 20 ns;
-- all data is transmitted to endpoint_test
--first package
REPLY_DATAREADY_IN(1) <= '1';
REPLY_DATA_IN(31 downto 16) <= x"0039";
REPLY_PACKET_NUM_IN(5 downto 3) <= "100";
wait for 20 ns;
REPLY_DATAREADY_IN(1) <= '1';
REPLY_DATA_IN(31 downto 16) <= x"8200";
REPLY_PACKET_NUM_IN(5 downto 3) <= "000";
wait for 10 ns;
REPLY_DATAREADY_IN(1) <= '1';
REPLY_DATA_IN(31 downto 16) <= x"5555";
REPLY_PACKET_NUM_IN(5 downto 3) <= "001";
wait for 10 ns;
REPLY_DATAREADY_IN(1) <= '1';
REPLY_DATA_IN(31 downto 16) <= x"ffff";
REPLY_PACKET_NUM_IN(5 downto 3) <= "010";
wait for 10 ns;
REPLY_DATAREADY_IN(1) <= '1';
REPLY_DATA_IN(31 downto 16) <= x"0d88";
REPLY_PACKET_NUM_IN(5 downto 3) <= "011";
wait for 10 ns;
--second package
REPLY_DATAREADY_IN(1) <= '1';
REPLY_DATA_IN(31 downto 16) <= x"0038";
REPLY_PACKET_NUM_IN(5 downto 3) <= "100";
wait for 10 ns;
REPLY_DATAREADY_IN(1) <= '0';
wait for 10 ns;
REPLY_DATAREADY_IN(1) <= '1';
REPLY_DATA_IN(31 downto 16) <= x"0000";
REPLY_PACKET_NUM_IN(5 downto 3) <= "000";
wait for 10 ns;
REPLY_DATAREADY_IN(1) <= '1';
REPLY_DATA_IN(31 downto 16) <= x"27f0";
REPLY_PACKET_NUM_IN(5 downto 3) <= "001";
wait for 10 ns;
REPLY_DATAREADY_IN(1) <= '1';
REPLY_DATA_IN(31 downto 16) <= x"0000";
REPLY_PACKET_NUM_IN(5 downto 3) <= "010";
wait for 10 ns;
REPLY_DATAREADY_IN(1) <= '1';
REPLY_DATA_IN(31 downto 16) <= x"5c66";
REPLY_PACKET_NUM_IN(5 downto 3) <= "011";
wait for 10 ns;
-- third package
REPLY_DATAREADY_IN(1) <= '1';
REPLY_DATA_IN(31 downto 16) <= x"0003";
REPLY_PACKET_NUM_IN(5 downto 3) <= "100";
wait for 10 ns;
REPLY_DATAREADY_IN(1) <= '1';
REPLY_DATA_IN(31 downto 16) <= x"0000";
REPLY_PACKET_NUM_IN(5 downto 3) <= "000";
wait for 10 ns;
REPLY_DATAREADY_IN(1) <= '1';
REPLY_DATA_IN(31 downto 16) <= x"0000";
REPLY_PACKET_NUM_IN(5 downto 3) <= "001";
wait for 10 ns;
REPLY_DATAREADY_IN(1) <= '1';
REPLY_DATA_IN(31 downto 16) <= x"0001";
REPLY_PACKET_NUM_IN(5 downto 3) <= "010";
wait for 10 ns;
REPLY_DATAREADY_IN(1) <= '1';
REPLY_DATA_IN(31 downto 16) <= x"0d88";
REPLY_PACKET_NUM_IN(5 downto 3) <= "011";
wait for 10 ns;
--end
REPLY_DATAREADY_IN(1) <= '0';
end process;
end DCA_bridge_tb_arch;
This diff is collapsed.
......@@ -6,9 +6,58 @@ add wave -noupdate /dca_bridge_tb/THE_DCA_Bridge/DCA_INIT_DATAREADY_OUT
add wave -noupdate /dca_bridge_tb/THE_DCA_Bridge/DCA_INIT_DATA_OUT
add wave -noupdate /dca_bridge_tb/THE_DCA_Bridge/DCA_INIT_PACKET_NUM_OUT
add wave -noupdate /dca_bridge_tb/THE_DCA_Bridge/DCA_INIT_READ_IN
add wave -noupdate /dca_bridge_tb/THE_DCA_Bridge/tx_fifo_q
add wave -noupdate /dca_bridge_tb/THE_DCA_Bridge/tx_fifo_data
add wave -noupdate /dca_bridge_tb/THE_DCA_Bridge/tx_fifo_wr
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/INIT_DATAREADY_IN
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/INIT_DATA_IN
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/act_init_port
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/init_pool_dataready_in
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/init_pool_data_in
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/init_pool_packet_num_in
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/INIT_READ_OUT
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/init_pool_data_out
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/init_pool_dataready_out
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/INIT_DATAREADY_OUT
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/INIT_DATA_OUT
add wave -noupdate /dca_bridge_tb/THE_DCA_Bridge/MAKE_RESET_OUT
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/init_has_read_from_pool
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/REPLY_READ_OUT
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/REPLY_DATAREADY_IN
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/REPLY_DATA_IN
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/REPLY_PACKET_NUM_IN
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/REPLY_DATA_OUT
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/reply_pool_empty
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/reply_pool_full
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/reply_pool_data_out
add wave -noupdate /dca_bridge_tb/THE_DCA_Bridge/DCA_REPLY_DATAREADY_IN
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/reply_pool_read_out
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/REPLY_READ_IN
add wave -noupdate -expand /dca_bridge_tb/wb_slave_out
add wave -noupdate /dca_bridge_tb/THE_DCA_Bridge/tx_data_out
add wave -noupdate /dca_bridge_tb/wb_slave_in
add wave -noupdate /dca_bridge_tb/THE_DCA_Bridge/dissect_current_state
add wave -noupdate /dca_bridge_tb/DCA_REPLY_DATA_IN
add wave -noupdate /dca_bridge_tb/DCA_REPLY_PACKET_NUM_IN
add wave -noupdate /dca_bridge_tb/DCA_REPLY_DATAREADY_IN
add wave -noupdate /dca_bridge_tb/THE_DCA_Bridge/tx_fifo_q
add wave -noupdate /dca_bridge_tb/THE_DCA_Bridge/tx_rd_size_ack
add wave -noupdate /dca_bridge_tb/THE_DCA_Bridge/tx_data_size_dca
add wave -noupdate /dca_bridge_tb/THE_DCA_Bridge/tx_fifo_wr
add wave -noupdate /dca_bridge_tb/THE_DCA_Bridge/tx_data_ctr
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/currentstate
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/reply_pool_data_in
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/reply_pool_packet_num_in
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/REPLY_combined_trm_F1
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/REPLY_combined_trm_F2
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/REPLY_combined_trm_F3
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/reading_trmF1
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/reading_trmF3
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/reading_trmF2
add wave -noupdate /dca_bridge_tb/THE_HUBLOGIC/reply_pool_dataready_in
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
quietly wave cursor active 0
WaveRestoreCursors {{Cursor 1} {1712110 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 317
configure wave -valuecolwidth 100
configure wave -justifyvalue left
......@@ -23,4 +72,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {0 ps} {207670 ps}
WaveRestoreZoom {1804490 ps} {1935330 ps}
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